Low-voltage green transistor using hetero-tunneling

Abstract

A novel hetero-tunnel transistor (HtFET) with a heterostructure parallel to the dielectric interface is proposed for low-voltage (low-power) electronics. Its potential of scaling V dd down to 0.2V is examined with quantum mechanical tunneling theory. Data from high-K metal-gate, Si on Ge hetero-tunnel transistor verifies the HtFET concept.Introd uction A green transistor (gFET) that allows Vdd scaling to below 0.5V is highly desirable for reducing the power consumption of future ICs. Gated PN diode transistors with an alternative operating principle, band-to-band tunneling, which is not limited by 60 mY/decade turn-off have long been explored [1,2]. Achieving large Ion at low Vdd is a great challenge. Fig. 1 shows a gFET that provides a large Ion and low tum-on voltage, Von, as shown by TCAD simulated I d -Vg in Fig. 2 [3]. Vg reverse biases the N+/P+ junction through capacitive coupling and thus causes valence electrons to tunnel from P+ to the N+ pocket. The electrons so generated in the floating N+ pocket drift to the drain as the drain current. The large uniform tunneling area and field at the N+/P+ junction produce a large tunnel current, i.e. Ion. The N+ dopant dose is adjusted to keep Von close to 50mV as shown. Fig. 2 shows that reducing the E g of the tunnel junction material provides a needed path for Vdd scaling. Unfortunately, even Ge only allows scaling to 0.5V with large Ion. Further Vdd scaling requires ultra-low-E, low-effective-mass materials which have technology compatibility and low density-of-states issues.Hetero-Tunnel Transistor Concept Fig. 3 shows a new way to reduce V dd without ultra-low-E, low effective-mass materials. Tunneling occurs between a thin cap and the source material. For n-type hetero-tunnel transistor (HtFET) the cap material is chosen to have a larger electron affinity than the source material as illustrated in Fig. 4. Fig. 4 qualitatively illustrates that the E, offset at the junction of Si cap and Ge reduces the tunneling barrier height and width compared to Ge tunnel barrier. This is so in spite of the larger E g of the Si cap. Fig. 5 is the TCAD simulation results showing large electron generation rate in the Si cap and the mostly vertical tunneling path. V dd Reduction with HtFETUnfortunately commercial TCAD simulator (MEDICI) only provides quantitatively accurate homo-tunneling models. We have analyzed one-dimensional hetero-tunneling current using the WKB approximation and Franz two-band model [4]. Fig. 6 compares the decay constants along the Si/Ge tunnel path and the Ge tunnel path. Note the lower decay constant in Si/Ge case than Ge in spite of silicon's larger E g • Fig. 7(a) shows the effect of E, offsets on I d -Vg. Von is adjusted to the same low value because the N+ pocket dose option (see Fig. 1) can be used. Fig. 7(b) shows the V dd required to produce the same Ion as Ge tunnel transistor at V dd = 0.5 V. V dd of 0.2

Simulation of nanowire tunneling transistors: From the Wentzel–Kramers–Brillouin approximation to full-band phonon-assisted tunneling

“…It can be realized with low band gap materials such as InAs or with properly designed heterostructures such as Si-Ge where the band gap discontinuity between these two materials leads to an effective tunneling gap of only 0.3 eV. [5][6][7] To accelerate the development in TFETs, it is crucial that the selection of the material system and the design of the transistor structure are critically analyzed with computer aided design tools before experiments are extensively conducted. The Wentzel-Kramers-Brillouin ͑WKB͒ approximation to Zener tunneling 8 has been widely used for its simplicity and its readiness.…”

Current Enhancement of Green Transistors Compared with Conventional Tunnel Field-Effect Transistors

“…http://dx.doi.org/10.7567/JJAP.52.04CC27 model, 28,29) and the energy band diagrams show that the tunneling regions of the p-gFET and p-TFET are in the vertical and lateral directions, respectively. Therefore, the current of the p-TFET is not influenced by gate length, and the current of the p-gFET would increase with the thickness of the gate-to-source/drain overlap region, [1][2][3][4][5][6] as shown in Figs. 1(a 3 and the swing vs drain current in Fig.…”

“…The operation concept of a green field-effect transistors (gFETs) was proposed with modeling and simulation to achieve steep switching (<60 mV/dec at room temperature) and a higher gate-controlled band-to-band tunneling (BTBT) current than that of conventional tunnel field-effect transistors (TFETs) [1][2][3][4][5][6] in 2008. The unique BTBT carrier transport mechanism of TFETs changes the current more abruptly than the thermionic emission current in conventional MOSFETs.…”

(Invited) High-K Dielectrics / High-Mobility Channel MOSFETs

“…Therefore TFETs are considered potential candidates to replace conventional Si MOSFETs for low-power digital applications. Most reported results have been focused on Si and Ge based TFETs [17][18][19][20][21][22], which unfortunately exhibit low on-currents (Ion) due to the high tunneling barrier. III-V TFETs may achieve larger tunneling currents compared to Si TFETs due to the smaller bandgap and the smaller electron mass.…”