P-type tunneling-based high-driving-current green field-effect transistors (p-gFETs) with dopant segregation (DS) on bulk Si were successfully fabricated and developed. gFETs with the vertical band-to-band tunneling (BTBT) mechanism have a valid benefit for ∼25× ON current enhancement compared with tunneling field-effect transistors (TFETs) without sacrificing leakage current and subthreshold swing for CMOS scaling in future-generation transistors. Ni DS enhanced the amount of n+ dopant in the source/drain region and produced a steep junction profile, which improved the BTBT mechanism. The promising gFET with silicon-on-insulator-free (SOI-free) gFET can be compatible with current processes and solve the issues of cost and thermal dissipation.
The promising potential of tunneling FETs (TFETs) for steep switch behavior with gate controlled band-to-band tunneling (BTBT) mechanism has attracted much attention for supply voltage (V DD ) scaling and power consumption next generation CMOS [1, 2]. However, the challenge for TFETs is lower drive currents as compare with MOSFET due to a high conductance resistance while reverse bias. Tunneling FETs (TFETs) operates with band-to-band tunneling current that change with the channel potential more abruptly than thermionic emission current. In order to obtain high I ON without sacrificing I OFF, and the high-k dielectric and metal gate are integrated as gate stack. To obtain high quality and avoid crystallizing of high-K layer, the gate last process was performed in this work. For N-TFET, much works have been reported on the SS improvement [4, 5]. For P-TFET, Bhuwalka et al. reported the ambipolar working of vertical TFET with negative gate bias, which obtain SS < 60mV/dec [6, 7]. In this work, we will demonstrate HK/MG (high-K/metal gate) P-TFET with the gate last process, and discuss the anisotropic effect on (110) substrate.Standard 6 inch MOS based line and gate last process are employed for this study. First, the p + and n + regions for drain and source were defined and implanted on p type Si substrate (100) and (110), and were implanted by BF 2 (60keV, 4x10 15 cm -2 ) and P (90keV, 4x10 15 cm -2 ), respectively. The annealing process for dopant activation was performed by RTA in an N 2 ambient with 2 steps. The step 1 is 600 °C for 100 sec and step 2 is 650 °C for 30 sec. A physical thickness ~13 nm HfSiO x as gate dielectric by Metal Organic Chemical Vapor Deposition (MOCVD) and 200 nm TiN as metal gate by Physical Vapor Deposition (PVD) were deposited (Fig. 1). In order to improve the interface layer between Si substrate and HfSiO x , the annealing with 600 °C 30 sec before PVD was performed. The TiN and HfSiO x were defined by dry etching and dipping in diluted HF solution to accomplish metal gate at last process (Fig. 2).The C-V characteristics of MOSCAP on (100) and (110) orientation of Si substrate shows a significant shoulder, and indicates the trap formation as combination center for (110) TFET (Fig. 3). The EOT (equivalent oxide thickness) is ~ 7.2 nm by C max , and the dielectric constant of HfSiO 2 is about 10. The high dielectric constant is due to gate last process without thermal annealing of source/drain activation for gate last process. The extracted D it (interface trap density) by high-low frequency C-V method shows the value at mid-gap is 5×10 11 cm -2 eV -1 for (100) and 1×10 12 cm -2 eV -1 for (110), respectively (Fig. 4). The channel direction is defined for band to ban tunneling (BTBT) on (100)&(110) orientation (Fig. 5). The transfer characteristics I DS -V GS of P-TFET on (100) and (110) substrate shows > 10 5 ON/OFF ratio (Fig. 6). The threshold voltage (V T ) of the TFET has been extracted based on the constant current method with I DS =10 -9 A/µm for V DS = -1 V. The output charact...
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