The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability current (I WR ) of 33 mA along with a low leakage current (I LEAK ) of 2 pA at a supply voltage (V DD ) of 0.9 V for cell and pullup ratios of 1. Results offer a new opportunity to design future SRAM cells with nanoscale JL MOSFETs.Introduction: Lateral doping gradient or abruptness of source/drain (S/D) extension regions is a key process/device parameter which significantly impacts the S/D series resistance as well as short-channel effects (SCEs) in nanoscale MOS devices and is a crucial technological factor limiting device scaling into the nanoscale regime. To overcome the technological difficulties in the formation of ultra-sharp S/D extension regions in nanoscale devices, the concept of the junctionless (JL) MOS transistor in silicon-on-insulator (SOI) and bulk technologies has been recently reported [1][2][3]. The JL transistor is an MOS device where the channel doping is the same as that of heavily doped S/D regions. The use of identical doping in the S/D and channel regions circumvents the necessity of controlling S/D gradients in the extension regions near the gate edge. In this work we analyse the performance of a 6T SRAM cell comprising JL MOSFETs and demonstrate its superiority over conventional 6T SRAM with inversion mode devices.