Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

Collaert, N.; Arnim, K. von; Rooyackers, R.; Vandeweyer, T.; Mercha, A.; Parvais, B.; Witters, L.; Nackaerts, A.; Sánchez, Efrain Altamirano; Demand, M.; Hikavyy, Andriy; Demuynck, S.; Devriendt, K.; Bauer, F.; Ferain, I.; Veloso, A.; Meyer, K. De; Biesemans, S.; Jurczak, M.

doi:10.1109/icicdt.2008.4567246

Cited by 18 publications

(9 citation statements)

References 6 publications

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“…Fig. 9(d) shows the different SNM values for DL-DGFET 6T SRAM cell along with IM devices available in [24]- [28]. The SNM values (0.181 V dd ) for DL-DGFETs at gate length of 20 nm shows potential for low power digital applications.…”

Section: B 6t-sram Cell Simulationmentioning

confidence: 92%

“…In general, an SRAM cell operates in three different states: 1) standby; 2) write; and 3) read. As SRAM cell being most vulnerable to noise during read operations [24]- [26], therefore we estimated the RSNM as well as hold SNM for both devices. The RSNM from both transfer characteristics are extracted by square fitting method that is the largest square to be fitted in between the overlapped plot of SRAM cell dc and its inverse characteristics.…”

Section: B 6t-sram Cell Simulationmentioning

confidence: 99%

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Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications

Sahu

Singh

2015

IEEE Trans. Electron Devices

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In this paper, we report the potential benefits of dopingless double-gate field-effect transistor (DL-DGFET) designed on ultrathin silicon on insulator film for low power applications. The simulation results show that the proposed device exhibits higher ON current and less sensitivity toward device parameter variation compared with highly doped junctionless (JL) DGFET. The constraints of high metal gate workfunction of JL device are also relaxed using midgap materials as a gate electrode in the DL-DGFETs. Sensitivity analysis shows that the DL-DGFET exhibits least sensitivity to device parameter variation especially gate length due to suppression of short-channel effects. The DL-DGFET also shows lower static power dissipation in OFF state and lower intrinsic delay in ON state. The mixed-mode simulation of 6T-static random access memory cell using DL-DGFET shows impressive read and hold noise margins of 147 and 352 mV at V DD = 0.8 V for ultralow power applications. The possible fabrication process flow of DL-DGFET is also proposed.

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Section: B 6t-sram Cell Simulationmentioning

confidence: 92%

Section: B 6t-sram Cell Simulationmentioning

confidence: 99%

Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications

Sahu

Singh

2015

IEEE Trans. Electron Devices

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“…This can be exploited at the layout level for circuit area optimization [8]. Parasitic capacitances and access resistances must also be closely monitored since both are strongly linked to the device architectures and isolation schemes (SOI BOX vs. STI) [9].…”

Section: Introductionmentioning

confidence: 99%

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

Chiarella

Witters

Mercha

et al. 2010

Solid-State Electronics

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123

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“…As shown in Fig. 3c, the proposed JL SRAM design achieves SNM values significantly higher than published [6][7][8][9] for inversion mode (IM) FinFET-based SRAM cells. While performance metrics in IM devices can be improved by adopting an underlap S/D design in which S/D doping concentration sharply decreases by 5 decades i.e.…”

Section: Junctionless 6t Sram Cellmentioning

confidence: 81%

Junctionless 6T SRAM cell

et al. 2010

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The design of a 6T SRAM cell with 20 nm junctionless (JL) MOSFETs is reported. It is shown that a 6T SRAM cell designed with JL MOSFETs achieves a high static noise margin (SNM) of 185 mV, retention noise or hold margin (RNM) of 381 mV and writability current (I WR ) of 33 mA along with a low leakage current (I LEAK ) of 2 pA at a supply voltage (V DD ) of 0.9 V for cell and pullup ratios of 1. Results offer a new opportunity to design future SRAM cells with nanoscale JL MOSFETs.Introduction: Lateral doping gradient or abruptness of source/drain (S/D) extension regions is a key process/device parameter which significantly impacts the S/D series resistance as well as short-channel effects (SCEs) in nanoscale MOS devices and is a crucial technological factor limiting device scaling into the nanoscale regime. To overcome the technological difficulties in the formation of ultra-sharp S/D extension regions in nanoscale devices, the concept of the junctionless (JL) MOS transistor in silicon-on-insulator (SOI) and bulk technologies has been recently reported [1][2][3]. The JL transistor is an MOS device where the channel doping is the same as that of heavily doped S/D regions. The use of identical doping in the S/D and channel regions circumvents the necessity of controlling S/D gradients in the extension regions near the gate edge. In this work we analyse the performance of a 6T SRAM cell comprising JL MOSFETs and demonstrate its superiority over conventional 6T SRAM with inversion mode devices.

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Low-voltage 6T FinFET SRAM cell with high SNM using HfSiON/TiN gate stack, fin widths down to 10nm and 30nm gate length

Cited by 18 publications

References 6 publications

Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications

Potential Benefits and Sensitivity Analysis of Dopingless Transistor for Low Power Applications

Benchmarking SOI and bulk FinFET alternatives for PLANAR CMOS scaling succession

Junctionless 6T SRAM cell

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