Low-temperature integrated process below 500°C for thin Ta/sub 2/O/sub 5/ capacitor for giga-bit DRAMs

Takaishi, Y.; Sakao, M.; Kamiyama, Satoshi; Suzuki, H.; Watanabe, Heiji

doi:10.1109/iedm.1994.383294

Cited by 8 publications

(6 citation statements)

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“…[1][2][3][4][5] Ta 2 O 5 has good compatibility with microelectronic processing but has a relatively low dielectric constant, with the opposite being the case for BST. To overcome this problem, a variety of different dielectric materials, such as Ta 2 O 5 and Barium Strontium Titanate (BST), are presently being actively studied for their possible use in applications such as DRAM's.…”

Section: Introductionmentioning

confidence: 99%

Dielectric properties of TiO₂–Nb₂O₅ crystallographic shear structures

et al. 1996

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The dielectric constants (K) have been measured near ambient temperature for polycrystalline bulk ceramics of the crystallographic shear compounds TiNb 24 O 62 , Ti 2 Nb 10 O 29 , and TiNb 2 O 7 . These show enhanced K's over Nb 2 O 5 and TiO 2 , with the 2 : 10 : 29 phase displaying an ambient temperature K of approximately 130. We also report the effects of partial substitution of Nb by Ta. In general, the dielectric constants are enhanced for 5-10% Ta substitution, with the detailed behavior differing for the three phases.

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Section: Introductionmentioning

confidence: 99%

Dielectric properties of TiO₂–Nb₂O₅ crystallographic shear structures

et al. 1996

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“…From the above considerations, one can find many candidates for metal gate materials published in the literature [4][5][6][7][8]. Some of these materials are Ti, Ta, W, Mo, Al, Pt, TiN, TaN, WN, MoN, NbN or gate stacks such as WITiN, polySi/TiN, poly/Si/WN, WSix/TiN.…”

Section: Work Function and Mosfet Threshold Voltagementioning

confidence: 98%

Metal gates for advanced CMOS technology

Maiti

Tobin

1999

SPIE Proceedings

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This paper will provide an overview of the emerging trends in metal gate solutions for advanced CMOS technology. Performance enhancement in silicon-based CMOS technology through MOSFET scaling has shown some limitations with the current polysilicon gate electrode. Replacing polysilicon gate electrode by metal appears to be promising. However, the choice of the metal gate material depends on its work function (single or dual metal gates), thermal/chemical stability with surrounding materials, process integration (conventional or inlaid approach), deposition process, resistivity, and eventually performance, reliability and future scaling. This paper will discuss some of the results published in the literature that address some of these issues and propose future directions. Single mid-gap metal gate approach appears to be simpler from an integration point of view but achieving low MOSFET threshold voltage is a concern. Some channel engineering approaches have been reported to address this issue. Dual metal gate approach with work function similar to n and p doped poly-Si appears ideal, although processing complexity could be a hindrance. Also the need for inlaid gate integration could be enhanced because of thermal/chemical stability effects of metal gate electrode with underlying gate dielectric, the inability to etch new materials or to reduce device instability due to film stress as in the conventional approach. The performance improvement of CMOS devices has been estimated with metal gates along with reliability issues.

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“…Many researchers have studied the effect of a number of annealing techniques such as the use of dry oxygen, ultraviolet generated ozone and plasma as well as two step process of rapid thermal annealing for crystallization of tantalum oxide films [4,5]. Recently a method for enhancing the crystallinity of these films has been reported by introducing deuterium oxide as sputtering gas [6]. Various thin film deposition techniques such as thermal oxidation, dc/rf sputtering, pulsed laser deposition, sol gel process and chemical vapor deposition were employed for preparation of tantalum oxide films.…”

Section: Introductionmentioning

confidence: 99%

Heat treatment induced structural and optical properties of rf magnetron sputtered tantalum oxide films

Chandra

Rao

Uthanna³

2007

Cryst. Res. Technol.

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Rf magnetron sputtering technique was employed for preparation of tantalum oxide films on quartz and crystalline silicon (111) substrates held at room temperature by sputtering of tantalum in an oxygen partial pressure of 1x10 -4 mbar. The films were annealed in air for an hour in the temperature range 573 -993 K. The effect of annealing on the chemical binding configuration, structure and optical absorption of tantalum oxide films was systematically studied.

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Low-temperature integrated process below 500°C for thin Ta/sub 2/O/sub 5/ capacitor for giga-bit DRAMs

Cited by 8 publications

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Dielectric properties of TiO₂–Nb₂O₅ crystallographic shear structures

Dielectric properties of TiO₂–Nb₂O₅ crystallographic shear structures

Metal gates for advanced CMOS technology

Heat treatment induced structural and optical properties of rf magnetron sputtered tantalum oxide films

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Low-temperature integrated process below 500°C for thin Ta/sub 2/O/sub 5/ capacitor for giga-bit DRAMs

Cited by 8 publications

References 0 publications

Dielectric properties of TiO2–Nb2O5 crystallographic shear structures

Dielectric properties of TiO2–Nb2O5 crystallographic shear structures

Metal gates for advanced CMOS technology

Heat treatment induced structural and optical properties of rf magnetron sputtered tantalum oxide films

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Product

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Dielectric properties of TiO₂–Nb₂O₅ crystallographic shear structures

Dielectric properties of TiO₂–Nb₂O₅ crystallographic shear structures