Low-power system-on-chip architecture for wireless LANs

Abstract

The authors present the architecture of a low-power system-on-chip (SoC) that implements baseband processing as well as the medium access control and data link control functionalities of a 5 GHz wireless system. The design is based on the HIPERLAN/2 wireless LAN standard, but it also covers critical processing requirements of the IEEE 802.11a standard. The options, constraints and motivations for the taken design decisions are presented, and the followed design steps, starting from the system specifications up to the architecture definition and the system implementation, are explained. The system's functionality covers both mobile terminal and access point devices. A critical design task in such systems is the assignment of the target system's tasks on the different types of processing elements available. Processor cores, dedicated hardware as well as memory elements and advanced bus architectures are used in order to achieve the target implementation. The architecture is targeted for a low-power SoC platform, due to the fact that power consumption is a critical parameter in electronic portable system design where excess power dissipation can lead to expensive and less reliable systems. A system prototype has been developed on a FPGA-based platform (including microprocessor modules). This FPGA-based prototype is currently being migrated to a SoC, which requires that the treatment of important issues such as clock handling, synthesis, testability and debugging is addressed.

Simultaneous Memory and Bus partitioning for SoC architectures.

“…We propose a new genetic algorithm based search technique for simultaneously partitioning the bus and on-chip memories for generating a power-efficient configuration based on the application characteristics. Our approach is primarily targeted towards application-specific SoCs [LB04,GCFOO], such as those developed in wireless LAN baseband processing, xDSL modems, low-level pixel processing for HDTV, etc.…”