Low power SRAM cell design for FinFET and CNTFET technologies

Delgado-Frias, J.G.; Zhang, Zhe; Turi, Michael A.

doi:10.1109/greencomp.2010.5598266

Cited by 20 publications

(12 citation statements)

References 18 publications

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“…FinFET is an emerging technology which is proving to be a deserving candidate to replace the present CMOS technology [9]. The basic structure of FinFET is shown in Figure 3.…”

Section: Basic Structure Of Finfet and Its Characteristicsmentioning

confidence: 99%

“…We need some promising devices which can replace the traditional CMOS, as CMOS is reaching its scaling limits. With the advent of the carbon nanotube (CNT) based field effect transistor (CNFET) technology, it is desirable to integrate the proposed circuit with this new technology which can offer additional advantages [9]. CNFET is one of the promising candidates which have proven their worth in terms of speed and power as compared to MOS transistors in the nanoscale regime [12].…”

Section: Cnfet Structure and Its Characteristicsmentioning

confidence: 99%

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Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application

Dwivedi

Urma

Islam

2015

Active and Passive Electronic Components

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This paper proposes a circuit capable of incorporating buffered delays in the order of picoseconds. To study our proposed circuit in the profound way, we have also explored our proposed circuit using emerging technologies such as FinFET and CNFET. Comparisons between these technologies have been made in terms of different parameters such as duration of incorporated delays (pulse width) and its variability with supply voltages. Further, this paper also proposes a trigger pulse generator by utilizing proposed buffered delay circuit as its basic element. Parametric results obtained for the proposed trigger pulse generator match different application specific requirements. These applications are also mentioned in this paper. The proposed trigger pulse generator requires very low supply voltage (700 mV) and also proves its effectiveness in terms of tunability of pulse width of the generated pulses. The modeling of the circuit has been done using Verilog and the simulation results are extensively verified using SPICE.

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“…FinFET is an emerging technology which is proving to be a deserving candidate to replace the present CMOS technology [9]. The basic structure of FinFET is shown in Figure 3.…”

Section: Basic Structure Of Finfet and Its Characteristicsmentioning

confidence: 99%

Section: Cnfet Structure and Its Characteristicsmentioning

confidence: 99%

Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application

Dwivedi

Urma

Islam

2015

Active and Passive Electronic Components

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“…In recent decades, many efforts have been made by researchers to offer optimum designs for bitcell. They declared that thanks to the CNTs, CNTFETs have been considered as a promising alternative for Complementary Metal Oxide Semiconductors (CMOSs) in low power SRAMs [10–75], however, CNFET fabrication process still has some imperfections, including the presence of metallic carbon nanotubes ( m ‐CNTs), imperfect m ‐CNT removal processes, chirality drift, CNT doping variations, and density fluctuations, etc. [76–79].…”

Section: Introductionmentioning

confidence: 99%

“…[76–79]. Some of them exhibited comparative works to show the advantages of CNTFETs over CMOSs and FinFETs in bitcells due to extensive electrical properties of CNTs and excellent characteristics of CNTFETs [42–61]. They also reported that bitcells suffered from leakage power [10, 12, 36, 66, 67], Delay [36, 66–69], worse Read SNM [34, 49, 52, 66], negative impacts of nearthreshold supply voltage on delays and SNM [41, 68], subthreshold leakage currents [57], etc., and suggested different techniques, such as ‘decoupled R/W BLs’ [34–47, 66, 68] and ‘power‐gating’ [41, 42, 63–65], to solve those problems.…”

Section: Introductionmentioning

confidence: 99%

Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell

Shahrabadi

2022

IET Circuits, Devices & Syst

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Recently, several studies were done on SRAM bitcells at different supply‐voltages; upper, near or lower to threshold voltage. To the best of the author's knowledge, none of them discussed at threshold supply‐voltage with proper subthreshold operations and Nano/Pico power‐dissipations, hence this paper decides to investigate challenges and solutions of designing at VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ = Vboldtboldh ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$, because this voltage will lead to having lower power consumptions. This research applies power‐gating technique to adjust VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ on Vboldtboldh ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$, and also utilises output‐inverter to set Logic 1 at VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$. Although ‘power‐gating’ and ‘output‐inverter’ were used in other works, this study renders specific points about them. In fact, the ability of power‐gating technique in adjusting VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$ on Vboldtboldh ${\mathbf{V}}_{\mathbf{t}\mathbf{h}}$ without any instabilities in bitcell operation was not reported before, as well as, the idea of employing output‐inverter in read path for setting Logic‐1 at VboldDboldD ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}$. It also proposed SNM% as a useful figure‐of‐merit. The goal of this study is not to present new circuits for bitcell, but is to investigate challenges and solutions of working under ‘VboldDboldD=Vboldtboldh ${\mathbf{V}}_{\mathbf{D}\mathbf{D}}={\mathbf{V}}_{\mathbf{t}\mathbf{h}}$’ which these solutions can lead to having an optimum bitcell.

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“…These effects will considerably reduce its potential for high performance applications in near future. As a result, there has been tremendous interest in development of new technologies which include single electron transistor, fin-field effect transistor and Carbon nanotube field-effect transistor (CNTFET) (Abu El-Seoud, El-Banna, & Hakim, 2007;Delgado-Frias, Zhang, & Turi, 2010). Among these, CNTFET could be the possible successor to silicon MOSFET, due to its unique 1-D band structure, near-ballistic transport operation and low OFF current characteristics (Hashempour & Lombardi 2008;Rahman, Guo, Datta, & Lundstrom, 2003;Lin, Appenzeller, Knoch, & Avouris, 2005;Akturk, Pennington, Goldsman, & Wickenden, 2007).…”

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confidence: 95%

Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

Murotiya

Gupta

2015

International Journal of Electronics

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This paper proposes a hardware efficient low power 2-bit ternary arithmetic logic unit (TALU) design in carbon nano tube field effect transistor (CNTFET) technology. The proposed TALU architecture combines Adder-Subtractor and Ex-OR cell in one cell, thereby it reduces number of transistors by 71% in comparison with other TALU architecture. Further, the proposed TALU is optimized at transistor level with a new pass-transistor logic based encoder circuit. Hspice simulation results show that the proposed design attains great advantages in power and power-delay product for addition and multiplication operations than reported designs. For instant, at power supply of 0.9 V, the proposed TALU consumes on average 91% and 95% less energy compared to their existing counterparts, for addition and multiplication operations, respectively.

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Low power SRAM cell design for FinFET and CNTFET technologies

Cited by 20 publications

References 18 publications

Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application

Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application

Challenges and solutions of working under threshold supply‐voltage, for CNTFET‐based SRAM‐bitcell

Hardware-efficient low-power 2-bit ternary ALU design in CNTFET technology

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