Trigger Pulse Generator Using Proposed Buffered Delay Model and Its Application

Abstract

This paper proposes a circuit capable of incorporating buffered delays in the order of picoseconds. To study our proposed circuit in the profound way, we have also explored our proposed circuit using emerging technologies such as FinFET and CNFET. Comparisons between these technologies have been made in terms of different parameters such as duration of incorporated delays (pulse width) and its variability with supply voltages. Further, this paper also proposes a trigger pulse generator by utilizing proposed buffered delay circuit as its basic element. Parametric results obtained for the proposed trigger pulse generator match different application specific requirements. These applications are also mentioned in this paper. The proposed trigger pulse generator requires very low supply voltage (700 mV) and also proves its effectiveness in terms of tunability of pulse width of the generated pulses. The modeling of the circuit has been done using Verilog and the simulation results are extensively verified using SPICE.

A Compact Low Power High Frequency Pulse Generator

“…The proposed trigger pulse generator consumes 1.502 µW of power to produce high frequency trigger pulse of precise pulse width of 92.35 ps. Thus, the power consumption is reduced to a satisfactory level as compared to circuits mentioned in [3] and [9] mainly because of the minimum number of transistors in the proposed design.…”

“…In other design mentioned in [3], [9] utilizes a buffer delay circuit consisting of 12T which increases the complexity of the mentioned design. The trigger pulse circuit proposed in this paper requires only 12 transistors (12T) to implement the whole circuit-level model which is very less as compared to the 42T based design presented in [3], [9].…”

“…The trigger pulse circuit proposed in this paper requires only 12 transistors (12T) to implement the whole circuit-level model which is very less as compared to the 42T based design presented in [3], [9]. Similar approach mentioned in [3] requires CNFETs to implement the design.…”

“…In general, the delay-introducing circuits can be classified in different families such as transmission gate based model [5], cascaded inverter based model [5], [6], voltage controlled based model [5][6][7][8] and hybrid cascaded inverter based model [3], [9]. The circuit diagram of these delay-introducing elements is shown in Fig.…”

“…Finally, the hybrid cascaded inverter based model mentioned in [3], [9], provides a buffered delay output with 12T to implement the design as shown in Fig. 1 (k).…”