Low power radiation tolerant VLSI for advanced spacecraft

Benz, H. F.; Gambles, J.W.; Whitaker, S.; Hass, K.J.; Maki, G.K.; Yeh, Pen-Shu

doi:10.1109/aero.2002.1035413

Cited by 10 publications

(2 citation statements)

References 5 publications

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“…The SoC is self-powered and contains its own power management, processing units and up-/downlink, and consumes 6.45 µW with its digital logic operating at a supply voltage of 0.5 V. Supply voltage scaling and body-biasing techniques have also attracted the attention of space electronics. The CMOS Ultra-Low Power Radiation Tolerant (CULPRiT) program found that up to 36x power savings were possible by scaling the supply voltage from 3.3 V to 0.5 V in a 0.35 µm CMOS technology [24]. A microcontroller designed using the CULPRiT techology showed up to two orders of magnitude better radiation tolerance than similar non-radiation tolerant microcontrollers, despite operating at a supply voltage of 0.5 V [25].…”

Section: Low-power Cmosmentioning

confidence: 99%

Low-power subthreshold to above threshold level shifters in 90nm and 65nm process

Hasanbegovic

Aunet

2011

Microprocessors and Microsystems

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Section: Low-power Cmosmentioning

confidence: 99%

Low-power subthreshold to above threshold level shifters in 90nm and 65nm process

Hasanbegovic

Aunet

2011

Microprocessors and Microsystems

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“…However, the interest for low power exists also in high reliability application areas such as space applications [1], [2]. The obvious reason for low power electronics being attractive in space applications is the limited power budget in spacecraft, for example when the power supply is dependent on solar cells.…”

Section: Introductionmentioning

confidence: 99%

Supply Voltage Dependency on the Single Event Upset Susceptibility of Temporal Dual-Feedback Flip-Flops in a 90 nm Bulk CMOS Process

Hasanbegovic

Aunet

2015

IEEE Trans. Nucl. Sci.

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In this paper we investigate the efficiency of using temporal and spatial hardening techniques in flip-flop design for single event upset (SEU) mitigation at different supply voltages. We present three novel SEU tolerant flip-flop topologies intended for low supply voltage operation. The most SEU tolerant flip-flop among the proposed flip-flop topologies shows ability of achieving maximum SEU cross-section below cm bit (no SEUs detected) at 500 mV supply voltage, cm bit at 250 mV supply voltage, and cm bit at 180 mV supply voltage. When scaling the supply voltage from 1 V down to 500 mV, 250 mV and 180 mV, the proposed flip-flops achieve at least , and (respectively) reduction in energy per transition compared to a Dual Interlocked Storage Cell based flip-flop when operated at a supply voltage of 1 V. The flip-flops have been designed and fabricated in a low-power commercial 90-nm bulk CMOS process and were tested using heavy ions with LET between MeV-cm mg and MeV-cm mg. Index Terms-Complimentary metal-oxide semiconductor (CMOS), flip-flop, low power, low voltage, radiation tolerant, single event transient (SET), single event upset (SEU).

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Low-power reconfigurable processor

Donohoe

Proceedings, IEEE Aerospace Conference

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Low power radiation tolerant VLSI for advanced spacecraft

Cited by 10 publications

References 5 publications

Low-power subthreshold to above threshold level shifters in 90nm and 65nm process

Low-power subthreshold to above threshold level shifters in 90nm and 65nm process

Supply Voltage Dependency on the Single Event Upset Susceptibility of Temporal Dual-Feedback Flip-Flops in a 90 nm Bulk CMOS Process

Low-power reconfigurable processor

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