Low-power reconfigurable processor

An Energy-Efficient Integrated Programmable Array Accelerator and Compilation Flow for Near-Sensor Ultralow Power Processing

“…These large-scale "array of processors" CGRAs are out of scope for ultra-low power, mW-level acceleration. Still there are reported in Table IX for comparison. NASA's Reconfigurable Data-Path Processor (RDPP) [12], and Field Programmable Processor Array (FPPA) [13] are targeted for low-power stream data processing for spacecrafts. These architectures rely on control switching [12] of data streams, and synchronous data flow computational model avoiding investment on memories and control.…”

“…Still there are reported in Table IX for comparison. NASA's Reconfigurable Data-Path Processor (RDPP) [12], and Field Programmable Processor Array (FPPA) [13] are targeted for low-power stream data processing for spacecrafts. These architectures rely on control switching [12] of data streams, and synchronous data flow computational model avoiding investment on memories and control. On the contrary, the IPA is tailored to achieve energy-efficient near sensor processing of data with workloads very different from the stream data processing.…”

“…In this paper, we focus on a CGRA architecture in the mW range (and below). Very few CGRA architectures have been pushed in this ultra-low power mission profile [36] [48] [12]. Our CGRA is designed to work as an accelerator of an ultra-low power PULP processor cluster [47], sharing L1 memory with the processors.…”

Trans_Proc: A Processor to Implement the Linear Transformations on the Image and Signal Processing and Its Future Scope

“…The papers proposing different designs in this domain are mainly of three types. The first category papers propose architectures to implement only a single category of linear transformations like FFT or FDCT [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. Since these implementation's primary focus is on speed so they are mainly implemented on ASIC.…”

“…Load data from the TP3 line to MIDREG 3.2Rout PE[5],MIDREG[3] Load data from MIDREG3 to input line of PE53 Load [D0],[PE 5] Load input data to D0 from input line of PE Load direct MIDREG4 Load data from the TP4 line to MIDREG 4. 5 Rout PE[5],MIDREG[4] Load data from MIDREG4 to input line of PE5 6 Load [D1],[PE 5] Load input data to D1 from input line of PE 5 7 Add [PE5] Add the content of D0 and 2's complement value of D1 and store the value in…”