2013 International Conference on Advanced Technologies for Communications (ATC 2013) 2013
DOI: 10.1109/atc.2013.6698126
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Low power optical transceivers for switched interconnect networks

Abstract: The power-consumption of network equipment is under ever-increasing scrutiny. As part of an ensemble project seeking to reduce power-consumption within data-centers 1 , this work focuses on reducing the power consumption of photonic transceivers for future fast power gated and/or optical switching networks. Utilising an open-source toolkit, we show that Serializer/Deserializer (SERDES) dominates power consumption of traditional optical transceivers. This result has particular implications for the modulation fo… Show more

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Cited by 2 publications
(4 citation statements)
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“…This value can be reduced by orders of magnitudes when shifting to more sophisticated low-power III/V-on-SOI photonic crystal technologies with nm-scale dimensions and power consumptions of a few mW [55], towards energy efficiencies of a few fJ/bit, comparable to electronics [6,20,21]. Meanwhile the use of the envisioned high-speed multi-bit optical ML architectures technology provides a possible path towards circumventing the use of power-hungry cost expensive power conversion at SERDES equipment, that can allocate up to half of the power consumption of a low power transceiver [24]. Additional power consumption benefits may also be obtained, when shifting to higher bitrates beyond 10 Gb/s [43] or even when exploiting the wavelength dimension for a single Access Gates shared among the multiplexed outputs of multiple optical RAMs [45].…”
Section: Future Challenges and Discussionmentioning
confidence: 99%
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“…This value can be reduced by orders of magnitudes when shifting to more sophisticated low-power III/V-on-SOI photonic crystal technologies with nm-scale dimensions and power consumptions of a few mW [55], towards energy efficiencies of a few fJ/bit, comparable to electronics [6,20,21]. Meanwhile the use of the envisioned high-speed multi-bit optical ML architectures technology provides a possible path towards circumventing the use of power-hungry cost expensive power conversion at SERDES equipment, that can allocate up to half of the power consumption of a low power transceiver [24]. Additional power consumption benefits may also be obtained, when shifting to higher bitrates beyond 10 Gb/s [43] or even when exploiting the wavelength dimension for a single Access Gates shared among the multiplexed outputs of multiple optical RAMs [45].…”
Section: Future Challenges and Discussionmentioning
confidence: 99%
“…To this end, electronic CAM speeds seem inefficient to keep up with the frantic optical linerates of 100 Gb/s and beyond [1]. This performance disparity has been placing an increasingly heavy load on the shoulders of electronic CAMs, enforcing energy-hungry, cost-expensive optoelectronic header conversions with subsequent data-rate down-conversion [22][23][24], in order to perform AL searches in the MHz-regime. Furthermore, the migration towards Software Defined Networks (SDN) and OpenFlow networks enforces a dynamic operation with frequent updates of network topologies and multiple real time changes in the RIB-list [25].…”
Section: Introductionmentioning
confidence: 99%
“…Despite a long history of optimization techniques for electronic mature electronic technology, state-of-theart electronic CAMs are still scaling in terms of frequency at a slow pace, limited by the well-known electronic memory bandwidth bottleneck [19,20] and seem incapable of keeping up with the increasing optical line rates [21]. This performance disparity is expected to continue impeding the routing system's performance, if relying solely on slow-performing CAMs, as the increasing optical line rates will further necessitate energy-hungry, cost-expensive optoelectronic header conversions with subsequent data-rate down-conversion [22][23][24], to realize AL searches in MHz-only performing electronic AL tables.Drawing from this memory bottleneck, there have been some recent advancements in photonic memories following different photonic integration approaches and architectural approaches to deliver speed, footprint, scalability and power consumption benefits [25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42]. However, the vast majority of photonic memory implementations so far reported have managed to develop only simplistic optical flip-flops (FFs) [32][33][34][35][36][37][38][39][40][41], that can only perform storing of the unitary bit.…”
mentioning
confidence: 99%
“…Despite a long history of optimization techniques for electronic mature electronic technology, state-of-theart electronic CAMs are still scaling in terms of frequency at a slow pace, limited by the well-known electronic memory bandwidth bottleneck [19,20] and seem incapable of keeping up with the increasing optical line rates [21]. This performance disparity is expected to continue impeding the routing system's performance, if relying solely on slow-performing CAMs, as the increasing optical line rates will further necessitate energy-hungry, cost-expensive optoelectronic header conversions with subsequent data-rate down-conversion [22][23][24], to realize AL searches in MHz-only performing electronic AL tables.…”
mentioning
confidence: 99%