Low-Power Null Convention Logic Multiplier Design Based On Gate Diffusion Input Technique

Metku, Prashanthi; Kim, Kyung Ki; Kim, Yong-Bin; Choi, Minsu

doi:10.1109/isocc.2018.8649885

Cited by 4 publications

(6 citation statements)

References 8 publications

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“…Among asynchronous circuit paradigms, NCL is a quasi-delay-insensitive (QDI) logic paradigm used in commercial applications and is chosen to design asynchronous circuits [4]. Many studies of NCLbased asynchronous circuits are implemented, such as the complementary metal-oxidesemiconductor circuit design of threshold gates with latency [5], of which comparisons of NCL threshold gate models [3] and some relevant studies can be found in [6][7][8][9][10][11][12]. In most of the studies mentioned above, authors synthesized their designs in one of three approaches.…”

Section: Introductionmentioning

confidence: 99%

A Methodology to Design Static NCL Libraries

Le-Thanh

Tri

Hoang

2022

JLPEA

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The Null Convention Logic (NCL) based asynchronous design technique has interested researchers because this technique had overcome disadvantages of the synchronous technique, such as noise, glitches, clock skew and power. However, using the NCL-based asynchronous design method is difficult for university students and researchers because of the lack of standard NCL cell libraries. Therefore, in this paper, a novel flow is proposed to design NCL cell libraries. These libraries are used to synthesize NCL-based asynchronous designs. We chose the static NCL cell library to illustrate the proposed design solution because this library is one of the most basic NCL libraries. Static NCL cells in this library are designed based on the Process Design Kit 45nm technology and are implemented by the Virtuoso and the Design Compiler (DC) tool. In addition, the Ocean script and Electronic Design Automation (EDA) environment are used for supporting designs and simulations. A complete library of 27 NCL cells was designed to serve for study and research. We also implemented synthesis for NCL full adders using this library and compared our synthesis results with the results of other authors. The comparison results indicated that our results were a 20% improvement on power consumption.

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Section: Introductionmentioning

confidence: 99%

A Methodology to Design Static NCL Libraries

Le-Thanh

Tri

Hoang

2022

JLPEA

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“…Multiplication is implemented using a multiplier, and the multiplier can be implemented in synchronous and asynchronous design styles. Many synchronous multipliers exist [1], and some non-robust [2][3][4][5][6][7][8][9][10][11][12], and few robust asynchronous multiplier designs [13][14][15][16] have been reported in the literature. References [2][3][4][5][6][7][8][9][10][11][12] discuss different asynchronous multiplier designs, which are either full-custom or semi-custom designs and make use of a non-robust, non-delay insensitive two-phase bundled-data asynchronous handshake protocol for data processing and communication.…”

Section: Introductionmentioning

confidence: 99%

“…References [13][14][15][16] discuss QDI array multipliers assuming an example 4×4 multiplication. Kim et al [13] compared 2-dimension pipelining versus 1-dimension pipelining for a QDI array multiplier realized using custom-designed null convention logic (NCL) gates.…”

Section: Introductionmentioning

confidence: 99%

“…It was concluded that the former pipelining approach leads to an improved speed than the latter albeit at the expense of increases in area and power. Metku et al [14] also custom-realized 4×4 QDI array multipliers using NCL gates which were designed using static CMOS and gate diffusion input (GDI) [24,25] techniques. They observed that the GDI design style results in reduced area and less average power compared to the static CMOS implementation.…”

Section: Introductionmentioning

confidence: 99%

“…They observed that the GDI design style results in reduced area and less average power compared to the static CMOS implementation. However, [13] and [14] involve manual (i.e., full-custom) transistor-level designs for each gate to realize the multipliers and they do not make use of a semi-custom design flow i.e., a standard digital cell library for synthesis.…”

Section: Introductionmentioning

confidence: 99%

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Speed, energy and area optimized early output quasi-delay-insensitive array multipliers

2020

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Multiplication is a widely used arithmetic operation that is frequently encountered in microprocessing and digital signal processing. Multiplication is implemented using a multiplier, and recently, QDI asynchronous array multipliers were presented in the literature utilizing delay-insensitive double-rail data encoding and four-phase return-to-zero (RTZ) handshaking and four-phase return-to-one (RTO) handshaking. In this context, this article makes two contributions: (i) the design of a new asynchronous partial product generator, and (ii) the design of a new asynchronous half adder. We analyze the usefulness of the proposed partial product generator and the proposed half adder to efficiently realize QDI array multipliers. When the new partial product generator and half adder are used along with our indicating full adder, significant reductions are achieved in the design metrics compared to the optimum QDI array multiplier reported in the literature. The cycle time is reduced by 17%, the area is reduced by 16.1%, the power is reduced by 15.3%, and the product of power and cycle time is reduced by 29.6% with respect to RTZ handshaking. On the other hand, the cycle time is reduced by 13%, the area is reduced by 16.1%, the power is reduced by 15.2%, and the product of power and cycle time is reduced by 26.1% with respect to RTO handshaking. Further, the RTO handshaking is found to be preferable to RTZ handshaking to achieve slightly improved optimizations in the design metrics. The QDI array multipliers were realized using a 32/28nm complementary metal oxide semiconductor (CMOS) process technology.

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Speed, Power and Area Optimized Monotonic Asynchronous Array Multipliers

Balasubramanian,

Mastorakis

2023

JLPEA

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Multiplication is a fundamental arithmetic operation in electronic processing units such as microprocessors and digital signal processors as it plays an important role in various computational tasks and applications. There exist many designs of synchronous multipliers in the literature. However, in the domain of Input–Output Mode (IOM) asynchronous design, there is relatively less published research on multipliers. Some existing works have considered quasi-delay-insensitive (QDI) asynchronous implementations of multipliers. However, the QDI asynchronous design paradigm, in general, is not area- and speed-efficient. This article presents an efficient alternative implementation of IOM asynchronous multipliers based on the concept of monotonic Boolean networks. The array multiplier architecture has been considered for demonstrating the usefulness of our proposition. The building blocks of the multiplier, such as the partial product generator, half adder, and full adder, were implemented monotonically. The popular dual-rail encoding scheme was considered for encoding the multiplier inputs and outputs, and four-phase return-to-zero handshaking (RZH) and return-to-one handshaking (ROH) were separately considered for communication. Compared to the best of the existing QDI asynchronous array multipliers, the proposed monotonic asynchronous array multiplier achieves the following reductions in design metrics: (i) a 40.1% (44.3%) reduction in cycle time (which is the asynchronous equivalent of synchronous clock timing), a 37.7% (37.7%) reduction in area, and a 4% (4.5%) reduction in power for 4 × 4 multiplication corresponding to RZH (ROH), and (ii) a 58.1% (60.2%) reduction in cycle time, a 45.2% (45.2%) reduction in area, and a 10.3% (11%) reduction in power for 8 × 8 multiplication corresponding to RZH (ROH). The multipliers were implemented using a 28 nm CMOS process technology.

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Low-Power Null Convention Logic Multiplier Design Based On Gate Diffusion Input Technique

Cited by 4 publications

References 8 publications

A Methodology to Design Static NCL Libraries

A Methodology to Design Static NCL Libraries

Speed, energy and area optimized early output quasi-delay-insensitive array multipliers

Speed, Power and Area Optimized Monotonic Asynchronous Array Multipliers

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