Low Power Magnetic Non-volatile Flip-Flops with Self-Time Logical Writing for High-End Processors

Udhayakumar, A.; Padma, S.

doi:10.1007/s00034-019-01108-y

Cited by 6 publications

(2 citation statements)

References 22 publications

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“…The proposed MTJ-based NVFF is also compared with existing MTJ-based NVFF. The existing NVFF includes conventional CMOS master and slave latches and an NV latch consisting of MTJ and its write and read circuitry (Roohi and DeMara, 2018; Udhayakumar and Padma, 2019; Munch et al , 2018; Jung et al , 2014). On a similar concept, Jung et al (2014) designed a master–slave DFF with MTJ inserted in the slave configuration.…”

Section: Simulation Resultsmentioning

confidence: 99%

Energy-efficient data retention in D flip-flops using STT-MTJ

Monga

Chaturvedi

Gurunarayanan

2020

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Purpose Emerging event-driven applications such as the internet-of-things requires an ultra-low power operation to prolong battery life. Shutting down non-functional block during standby mode is an efficient way to save power. However, it results in a loss of system state, and a considerable amount of energy is required to restore the system state. Conventional state retentive flip-flops have an “Always ON” circuitry, which results in large leakage power consumption, especially during long standby periods. Therefore, this paper aims to explore the emerging non-volatile memory element spin transfer torque-magnetic tunnel junction (STT-MTJ) as one the prospective candidate to obtain a low-power solution to state retention. Design/methodology/approach The conventional D flip-flop is modified by using STT-MTJ to incorporate non-volatility in slave latch. Two novel designs are proposed in this paper, which can store the data of a flip-flip into the MTJs before power off and restores after power on to resume the operation from pre-standby state. Findings A comparison of the proposed design with the conventional state retentive flip-flop shows 100 per cent reduction in leakage power during standby mode with 66-69 per cent active power and 55-64 per cent delay overhead. Also, a comparison with existing MTJ-based non-volatile flip-flop shows a reduction in energy consumption and area overhead. Furthermore, use of a fully depleted-silicon on insulator and fin field-effect transistor substituting a complementary metal oxide semiconductor results in 70-80 per cent reduction in the total power consumption. Originality/value Two novel state-retentive D flip-flops using STT-MTJ are proposed in this paper, which aims to obtain zero leakage power during standby mode.

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Section: Simulation Resultsmentioning

confidence: 99%

Energy-efficient data retention in D flip-flops using STT-MTJ

Monga

Chaturvedi

Gurunarayanan

2020

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“…Selection of appropriate flip‐flop topology is very essential, in the design of very large scale IC, such as microprocessors, micro controllers, many highly complex, and dense circuit chips 19,20 . However, factors such as good performance, ultra‐low power, number of transistor, clock load, robustness of design, power delay, and power‐area trade‐off are normally considered before selecting a specific flip‐flop design 21,22 . Nowadays, research has focused on advancing lower power and decreased variability flip‐flop circuits, particularly aiming low supply voltage operation 23,24 .…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of ultra‐low power 18T adaptive data track flip‐flop for high‐speed application

Mishra

Vaithiyanathan

Chopra

2021

Circuit Theory & Apps

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Summary This paper proposes a novel master slave (MS) flip‐flop design achieved by using only 18 transistors with a single‐phase clock and mixed topology. This design has lowest complexity, so flip‐flop basically focuses on the performance issue such as delay (TCQ) and average power consumption and compared with the other existing logic structured flip‐flops. The proposed circuit is implemented at 65‐nm Complementary Metal‐Oxide Semiconductor (CMOS), and 18‐nm finFET technology node using cadence virtuoso. The proposed flip‐flop architecture have outperformed transmission gate flip‐flop (TGFF) in terms of power (i.e., 74.52%). It is also showing improvement in terms of power as compared to 18‐transistor single‐phase clocking (18TSPC). This work also enhances the speed by reducing the delay minimum of 11.28% and PDP minimum of 37.18%. By using adaptive pass transistors topology to construct flip‐flop, the total area of the proposed flip‐flop reduces by a minimum of 4.78% with respect to 18TSPC, and also with the other flip‐flops reported in this paper. The proposed circuit can work properly within the frequency range up to 2‐GHz clock frequency. Monte Carlo simulations of Power and C to Q delay have been performed for 1000 samples.

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NVLCFF: An Energy-Efficient Magnetic Nonvolatile Level Converter Flip-Flop for Ultra-Low-Power Design

Morsali

Moaiyeri

2019

Circuits Syst Signal Process

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Low Power Magnetic Non-volatile Flip-Flops with Self-Time Logical Writing for High-End Processors

Cited by 6 publications

References 22 publications

Energy-efficient data retention in D flip-flops using STT-MTJ

Energy-efficient data retention in D flip-flops using STT-MTJ

Design and analysis of ultra‐low power 18T adaptive data track flip‐flop for high‐speed application

NVLCFF: An Energy-Efficient Magnetic Nonvolatile Level Converter Flip-Flop for Ultra-Low-Power Design

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