Directional antennas revolutionized modern day telecommunication by enabling precise beaming of radio and microwave signals with minimal loss of energy. Similarly, directional optical nanoantennas are expected to pave the way toward on-chip wireless communication and information processing. Currently, on-chip integration of such antennas is hampered by their multielement design or the requirement of complicated excitation schemes. Here, we experimentally demonstrate electrical driving of in-plane tunneling nanoantennas to achieve broadband unidirectional emission of light. Far-field interference, as a result of the spectral overlap between the dipolar emission of the tunnel junction and the fundamental quadrupole-like resonance of the nanoantenna, gives rise to a directional radiation pattern. By tuning this overlap using the applied voltage, we record directivities as high as 5 dB. In addition to electrical tunability, we also demonstrate passive tunability of the directivity using the antenna geometry. These fully configurable electrically driven nanoantennas provide a simple way to direct optical energy on-chip using an extremely small device footprint.
Surface-plasmon-polariton waves propagating at the interface between a metal and a dielectric, hold the key to future high-bandwidth, dense on-chip integrated logic circuits overcoming the diffraction limitation of photonics. While recent advances in plasmonic logic have witnessed the demonstration of basic and universal logic gates, these CMOS oriented digital logic gates cannot fully utilize the expressive power of this novel technology. Here, we aim at unraveling the true potential of plasmonics by exploiting an enhanced native functionality - the majority voter. Contrary to the state-of-the-art plasmonic logic devices, we use the phase of the wave instead of the intensity as the state or computational variable. We propose and demonstrate, via numerical simulations, a comprehensive scheme for building a nanoscale cascadable plasmonic majority logic gate along with a novel referencing scheme that can directly translate the information encoded in the amplitude and phase of the wave into electric field intensity at the output. Our MIM-based 3-input majority gate displays a highly improved overall area of only 0.636 μm2 for a single-stage compared with previous works on plasmonic logic. The proposed device demonstrates non-Boolean computational capability and can find direct utility in highly parallel real-time signal processing applications like pattern recognition.
Major obstacles in current CMOS technology, such as the interconnect bottleneck and thermal heat management, can be overcome by employing subwavelength-scaled light in plasmonic waveguides and devices. In this work, a plasmonic structure that implements the majority (MAJ) gate function is designed and thoroughly studied through simulations. The structure consists of three merging waveguides, serving as the MAJ gate inputs. The information of the logic signals is encoded in the phase of transmitted surface plasmon polaritons (SPP). SPPs are excited at all three inputs and the phase of the output SPP is determined by the MAJ of the input phases. The operating dimensions are identified and the functionality is verified for all input combinations. This is the first reported simulation of a plasmonic MAJ gate and thus contributes to the field of optical computing at the nanoscale.
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