No abstract

This paper presents a blueprint for a 10000TOPS/W matrix-vector multiplier for neural network inference based on Analog in-Memory Computing (AiMC), an energy efficiency at least 10x beyond ultimate digital implementations. The presented analysis connects circuit design with technology options and requirements. A compute array using pulse-width encoded activations and precharge-discharge summation line is used as circuit blueprint, key device requirements for this compute array are derived and 3 suited device options are discussed: SOT-MRAM, IGZO-based 2T1C DRAM gain cell, and projection PCM with separate write path.

In the context of neuromorphic computation, spintronic memristors are investigated for their use as synaptic weights. In this paper, we propose and experimentally demonstrate a resistive synaptic device based on ten magnetic tunnel junctions (MTJs) connected in a serial configuration. Our device exhibits multiple resistance levels, that supports its use as a synaptic element. It allows for two operating knobs: external magnetic field and voltage pulses (Spin-Transfer Torque). Moreover, it can be operated in different ways. When varying continuously the amplitude of the voltage pulse and/or the magnetic field, eleven resistance states can be reached. In contrast, if the initial state of the chain is reset between every step, a very large number of levels are reached. Ideally, a total of 2 N resistance levels could be accessible. This coincides well with the desired analog-like behavior in ideal memristors. Since this device consists of a scalable number of N MTJs, and MTJ technology is continuously optimized and improved, the proposed memristor shows promise as a scalable synapse solution for neuromorphic hardware implementations.

No abstract