Low-Power Level Shifter for Multi-Supply Voltage Designs

Lanuzza, Marco; Corsonello, Pasquale; Perri, Stefania

doi:10.1109/tcsii.2012.2231037

Cited by 87 publications

(55 citation statements)

References 13 publications

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“…Average normalized EDP of TSCWLS (with respect to WLS) is only 69%. Table 1 shows the results of the proposed design and comparison with other previously proposed designs from [6][7][8][9][10]13]. From the comparison, it can be seen that the proposed design exhibits best performance and [9].…”

Section: Post-layout Resultsmentioning

confidence: 99%

“…For a 0.2 V input signal, the normalized energy-delay-product (EDP) of TSCWLS, WLS, LS from [8] and LS from [9] is 1, 1.38, 1.01 and 1.27, respectively. Only the LS from [9] comes near TSCWLS in terms of EDP with a penalty of 1%.…”

Section: Post-layout Resultsmentioning

confidence: 99%

“…However, this design does not achieve highspeed performance. Use of multi-threshold technology has been proposed to strengthen the pull-up network and weaken the pull-down network [8,9]. As multi-V TH technology is not mainstream, its use is quite complex and expensive.…”

Section: Introductionmentioning

confidence: 99%

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A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror

2017

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Multiple voltage domains are commonplace in modern SoCs and level shifter (LS) circuits allow different voltage domains to be interfaced with each other. As the reduced supply voltages are extensively used in digital blocks for low-power operation, the conversion of sub-threshold voltage levels to full VDD signal becomes a particular problem. In this paper we present a new LS structure for the fast and energy-efficient conversion of extremely low voltage levels. The proposed LS is a two-stage structure consisting of a controlled Wilson current mirror and eliminates the negative feedback mechanism. Inverted output of the second stage controls the current through the first stage. If the input signal is logical high (VDDL) then the circuit will produce high output (VDDH) and the first stage is prepared to conduct the current for logical 0 input (0V). This improves the slew rate problem and enables fast and energy-efficient operation. Considering process corners at a 90-nm technology node, the proposed design reliably converts 150-mV input signal into 1 V output signal. Post-layout results show that the proposed LS exhibits a propagation delay of 16 ns, a total energy per transition of only 79 fJ, and a static power dissipation of 16.6 nW for a 200 mV input signal at 1-MHz, while loading 100 fF of capacitive load. ARTICLE HISTORY

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Section: Post-layout Resultsmentioning

confidence: 99%

Section: Post-layout Resultsmentioning

confidence: 99%

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A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror

2017

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“…In the designed level shifter circuit, the main focus was to reduce the power dissipation and the output delay by modifying the dimensions of the transistors. The dynamic power dissipation can be decreased by minimizing the size of the gate which in turn reduces both the width and the length of the transistor [16]. Different dimensions of the transistors width and length (W/L) were used to design the proposed circuit as described in table 1.…”

Section: Methodsmentioning

confidence: 99%

Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

Badal¹,

Reaz²,

Farayez³

et al. 2017

JESTR

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Level Shifter (LS) circuits are widely used as interfaces for multiple voltage domains in moderns ICs and System on Chips (SoCs). Low power dissipation and low delay are the main design considerations for high performance level shifters. This paper presents the design of a level shifter integrating new topological modifications to assure a wide range of voltage conversion with low power dissipation and low output delay. The presented level shifter is designed to take input signal of 1 V and convert that into an output signal of 1.8 V which is simulated in Silterra 0.13 µm CMOS process. The post layout simulation results show that the designed LS circuit has a significant low power dissipation of only 0.1449 nW and low output delay of 25.55 ps covering only 17.36× 14.560 µm2 chip area. Through detailed comparison with recently reported LS circuits, it has been shown that the proposed level shifter achieved a better performance in terms of power consumption, delay and compact chip size.

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“…This design avoids intermediate supply voltages, but does not achieve high-speed performance. Multi-threshold technology has also been used to strengthen and weaken the pull-down and pull-up network by using low-threshold and highthreshold devices respectively [6]. However, use of multi-threshold is complex and expensive.…”

Section: Introductionmentioning

confidence: 99%

Energy efficient low static-power voltage level shifter

Maroof

Sohail

Shin

2015

IEICE Electron. Express

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Level shifter circuits are necessary parts of modern SoCs, as they interface different voltage domain signals. This paper presents an energyefficient level up shifter capable of converting sub-threshold input signal to higher levels. The proposed design uses the feedback mechanism of a regulated gate cascode to achieve energy efficient operation. Once the desired output level is achieved, large static current does not flow, and static power is further minimized using a transistor stack. Implementing in a 90-nm process, post-layout simulation results show that the proposed level shifter has a propagation delay of 21.2 ns, a total energy-per-transition of only 77.5 fJ, and a static power dissipation of 7.2 nW.

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Low-Power Level Shifter for Multi-Supply Voltage Designs

Cited by 87 publications

References 13 publications

A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror

A fast and energy-efficient two-stage level shifter using the controlled Wilson current mirror

Design of a Low-power CMOS Level Shifter for Low-delay SoCs in Silterra 0.13 µm CMOS Process

Energy efficient low static-power voltage level shifter

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