Low-Power Issues for SoC

Лазоренко, Д. И.; Chemeris, Alexander

doi:10.1109/isce.2006.1689463

Cited by 5 publications

(5 citation statements)

References 5 publications

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“…P DYN is the summation of switching power (P SWI ) and short-circuit power (P SC ) [6]. Mathematically, total power consumption (P TOT ) of an IC can be represented as [1], [3], [4]:…”

Section: Power Dissipation In Cmos Circuitsmentioning

confidence: 99%

“…where C is the total capacitance, V DD is the supply voltage, f is the operating frequency, and αis the switching activity [3], [4].…”

Section: Power Dissipation In Cmos Circuitsmentioning

confidence: 99%

“…This has been the main driving factor for the applications enhancement in SoC design [1], [2], [4]. However, there are few challenges that need to be faced by integrated circuit (IC) designers.…”

Section: Introductionmentioning

confidence: 99%

“…Alternatively, most designers practice appropriate low power design techniques at different design levels to resolve the power issue. design techniques at each design levels with their respective percentages of power savings [2], [4]. This paper will be discussing on clock gating technique and its implementation on DMA.…”

Section: Introductionmentioning

confidence: 99%

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Clock Gating Implementation on Direct Memory Access

Gandi¹,

Ali²,

Sutanthavibul³

2012

IJCEE

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Abstract-This paper discusses about the implementation of a low power design technique, clock gating, on Direct Memory Access (DMA) at Register Transfer Level (RTL). Modification has been done to the existing clock gating circuitry by adding and utilizing the reset signal of a register as an additional enable pin. The modification approach and the method to identify appropriate clock gating candidates have been discussed. The power consumptions and few other factors including speed and area were estimated. The results were compared with two different methods of clock gating implementations, fine-grain clock gating and global clock gating. A total of 38% of dynamic power reduction has been achieved when both, global clock gating and fine-grain clock gating were implemented simultaneously.Index Terms-Clock gating, dynamic power,leakage power, and low power VLSI design.

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“…P DYN is the summation of switching power (P SWI ) and short-circuit power (P SC ) [6]. Mathematically, total power consumption (P TOT ) of an IC can be represented as [1], [3], [4]:…”

Section: Power Dissipation In Cmos Circuitsmentioning

confidence: 99%

“…where C is the total capacitance, V DD is the supply voltage, f is the operating frequency, and αis the switching activity [3], [4].…”

Section: Power Dissipation In Cmos Circuitsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Clock Gating Implementation on Direct Memory Access

Gandi¹,

Ali²,

Sutanthavibul³

2012

IJCEE

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“…Excessive power consumption can lead to thermal issues, reliability and complex power supply design [1]. Power saving can be tackled at different levels of the design cycle and research has shown the earlier in the cycle the more gain in terms of power reduction [2].…”

Section: Introductionmentioning

confidence: 99%

Architecture Level Power-Performance Tradeoffs for Pipelined Designs

Ali

Al-Hashimi

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Abstract-This paper presents a method to investigate powerperformance tradeoffs in digital pipelined designs. The method is applied at the architectural level of the design. It will be shown that addressing the tradeoffs at this level will result in significant savings in power consumption without impacting the performance. The reduction in power is obtained through reducing the number of registers used in implementing the pipeline stages. The method has been validated by synthesizing a floating-point unit with different pipeline stages and power consumption of the designs were obtained using industry standard tools. It is shown that it is possible to obtain up to 18% reduction in power without affecting the clock period and with less area.

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