Architecture Level Power-Performance Tradeoffs for Pipelined Designs

Ali, Haider; Al-Hashimi, Bashir M.

doi:10.1109/iscas.2007.378020

Cited by 4 publications

(3 citation statements)

References 8 publications

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“…Pipelining a design involves [48] the addition of registers to create stages with the aim of improving throughput when the pipeline is fully utilized. Crucially the location of the pipeline stage will dictate the number of registers required to implement the stage.…”

Section: B Pipeliningmentioning

confidence: 99%

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

Qadri¹,

Gujarathi²,

McDonald-Maier³

2009

JCP

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Abstract-The technological evolution has increased the number of transistors for a given die area significantly and increased the switching speed from few MHz to GHz range. Such inversely proportional decline in size and boost in performance consequently demands shrinking of supply voltage and effective power dissipation in chips with millions of transistors. This has triggered substantial amount of research in power reduction techniques into almost every aspect of the chip and particularly the processor cores contained in the chip. This paper presents an overview of techniques for achieving the power efficiency mainly at the processor core level but also visits related domains such as buses and memories. There are various processor parameters and features such as supply voltage, clock frequency, cache and pipelining which can be optimized to reduce the power consumption of the processor. This paper discusses various ways in which these parameters can be optimized. Also, emerging power efficient processor architectures are overviewed and research activities are discussed which should help reader identify how these factors in a processor contribute to power consumption. Some of these concepts have been already established whereas others are still active research areas.

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Section: B Pipeliningmentioning

confidence: 99%

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

Qadri¹,

Gujarathi²,

McDonald-Maier³

2009

JCP

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“…Many concepts of power minimization at the system level can be found in [3][4][5][6]. They are often related to the problems of high-level synthesis, presented, inter alia, in [7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

Logic Synthesis Strategy Oriented to Low Power Optimization

2021

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The article presents a synthesis strategy focused on low power implementations of combinatorial circuits in an array-type FPGA structure. Logic functions are described by means of BDD. A new form of the SWitch activity BDD diagram (SWBDD) is proposed, which enables a function decomposition to minimize the switching activity of circuits. The essence of the proposed idea lies in the proper ordering of the variables and cutting the diagram, ensuring the minimization of switching in the combination circuit. This article contains the results of experiments confirming the effectiveness of the developed concept of decomposition. They were performed on popular benchmarks using academic and commercial synthesis systems.

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“…Energy efficiency issues can be related to different levels of system synthesis. In the case of high-level synthesis [8][9][10][11][12], there are a number of methods to reduce power consumption, such as: effective hardware and software implementation of functions [13], temporary shutdown of individual modules or implementation of the circuit in the form of a GALS structure (Globally Asynchronous Locally Synchronous) [14]. However, in the case of low-level synthesis, the methods of reducing power consumption include: "power gating" [12], local reduction of the supply voltage [15,16], techniques related to local reduction of the frequency of the clock signal or its complete blocking ("clock gating") [17].…”

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confidence: 99%

Decomposition Approaches for Power Reduction

2023

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The article discusses a synthesis strategy aimed at reducing power consumption consumed by logic structures implemented in FPGAs. The essence of the method is to carry out multioutput function decomposition, which takes into account the problem of dynamic power reduction. The article presents several techniques leading to such a reduction: preliminary ordering of variables taking into account the probabilities of occurrence of the value 1 for individual variables, reduction of the number of LUTs by limiting the number of bound functions, and in particular bicoding or appropriate unicoding taking into account the need to reduce power for the implementation of multioutput functions. These techniques have been combined into a coherent synthesis strategy called PowerdekBDD, which is an extension of the DekBDD strategy, which is the result of many years of work in the area of logic synthesis using BDD graphs. The article contains the results of experiments confirming the effectiveness of the presented strategy.INDEX TERMS decomposition, FPGA, low power synthesis, switching activity, technology mapping I. INTRODUCTION

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Architecture Level Power-Performance Tradeoffs for Pipelined Designs

Cited by 4 publications

References 8 publications

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

Low Power Processor Architectures and Contemporary Techniques for Power Optimization – A Review

Logic Synthesis Strategy Oriented to Low Power Optimization

Decomposition Approaches for Power Reduction

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