Low‐power hybrid memristor‐CMOS spiking neuromorphic STDP learning system

Abstract

An electronic circuit that implements a neural network architecture with spike neurons was studied, proposed, and evaluated, primarily considering energy consumption. In this way, CMOS transistors were used to implement neurons, memristors were used to work as synapses, and the proposed network has a spike‐timing‐dependent plasticity (STDP) learning aspect. The validation of the circuit modules and the complete network architecture was performed using SPICE models. Since most data of company technologies is restricted, some universities provide predictive models to reproduce the real ones. In this paper, two types of Integrate and Fire Neuron (I&F) using 32 nm CMOS technology simulated in LTspice with BSIM4v4 model designed by Berkley University and applying predictive parameters provided by Predictive Technology Model (PTM) are presented. The simulation results obtained here reduces the bias voltage and the chip size to the most recent designs implemented. Finally, communication between neurons and synapses with STDP learning has been successfully simulated.

Bi-sigmoid spike-timing dependent plasticity learning rule for magnetic tunnel junction-based SNN

“…While many hardware implementations of SNNs focus on inference, online training remains a big challenge because of the lack of implementations that can dynamically update their weights in response to the changing environments that they are learning. Maranhão and Guimarães ( 2021 ) proposed a toy model with post-synaptic neuron spiking and memristive synapses that update in one direction only. Similarly, Andreeva et al ( 2020 ) used different CMOS neurons for input and output with memristive synapses.…”

“…The state-of-the-art SNN hardware implementations can be split into three categories: first, systems like CPUs, GPUs, and TPUs focused on computational complexity with high accuracy but high power use (Baji, 2017 ; Wang et al, 2020 , 2019 ); second, power-efficient CMOS-based engines such as TrueNorth (Merolla et al, 2014 ) and Loihi (Davies et al, 2018 ), which are constrained by memory bottlenecks; and finally, biologically plausible in-memory computing using non-volatile technology, yet lacking online learning capabilities (Maranhão and Guimarães, 2021 ; Lone et al, 2022 ). These approaches struggle to balance energy efficiency with the capability for online unsupervised learning.…”

Synaptic Control for Hardware Implementation of Spike Timing Dependent Plasticity

“…Whereas it is the on-line training which should be tackled in order to reduce energy consumption. The authors of [14] propose a toy model of a post-synaptic neuron spiking as a response to the activity of two pre-synaptic neurons, then the memrestive synapses update their state variable consequently, but in one direction only. Their training rule is lacking time dependence also, the output neuron spikes whenever it receives an activity.…”

A high‐capacity and nonvolatile spintronic associative memory hardware accelerator

“…Because of the fascinating capabilities of the human brain, such as parallel processing, error resilience (working with approximate data), and the most remarkable feature, learning capacity, bio-inspired computational systems have become highly successful [1][2][3]. Bio-inspired computational systems show great potential to overcome Von-Neumann-based computers' inefficiency in processing complex tasks, such as image processing and pattern association [4][5][6][7].…”