A high‐capacity and nonvolatile spintronic associative memory hardware accelerator

Rezaei, Masoud; Amirany, Abdolah; Moaiyeri, Mohammad Hossein; Jafari, Kian

doi:10.1049/cds2.12160

Cited by 6 publications

(1 citation statement)

References 43 publications

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“…By restricting both weights and activations to 1-bit precision, the system circumvents the necessity for complex and error-prone floatingpoint operations, which demand high levels of precision and stability in electronic systems. [59][60][61][62][63][64][65][66][67][68][69][70][71][72] This co-design strategy streamlines the optical realizations of computational tasks associated with BNNs. Optical components inherently suited for binary operations, like the XNOR gate, become pivotal in this architecture, facilitating efficient and accurate computations by directly manipulating the properties of light.…”

Section: Proposed Optical Binary Neural Network Acceleratormentioning

confidence: 99%

An efficient optical-based binary neural network hardware accelerator for harsh environments

Jahannia,

Ye,

Altaleb

et al. 2024

Silicon Photonics XIX

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Binarized neural networks offer substantial reductions in memory and computational requirements compared to full precision networks. However, conventional CMOS-based hardware implementations still face challenges with resilience for deployment in harsh environments like space. This paper proposes an optical XOR-based accelerator for binarized neural networks to enable low power and resilient operation. The optical logic gates rely on wavelength-specific intensity propagation rather than absolute intensity levels. This provides inherent robustness against fabrication process variations and high energy particle strikes. Simulations of an optical hardware prototype for XNOR-Net show the accelerator achieves 1.2 µs latency and 3.2 mW power. The binarized network maintained 2-4% accuracy degradation compared to the full precision baseline on MNIST and CIFAR-10. The proposed optical accelerator enables efficient and resilient deployment of binarized neural networks for harsh environment applications like spacecraft and satellites.

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Section: Proposed Optical Binary Neural Network Acceleratormentioning

confidence: 99%

An efficient optical-based binary neural network hardware accelerator for harsh environments

Jahannia,

Ye,

Altaleb

et al. 2024

Silicon Photonics XIX

View full text Add to dashboard Cite

show abstract

A reliable non‐volatile in‐memory computing associative memory based on spintronic neurons and synapses

Rezaei,

Amirany,

Moaiyeri

et al. 2024

Engineering Reports

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This article introduces an innovative non‐volatile associative memory (AM) that leverages spintronic synapses, employing magnetic tunnel junctions (MTJ) in conjunction with neurons constructed using carbon nanotube field‐effect transistors (CNTFETs). Our proposed design represents a significant advancement in area optimization and outperforms prior designs. We adopt MTJ‐based spintronic devices due to their remarkable attributes, including dependable reconfigurability and nonvolatility. Simultaneously, CNTFETs effectively address the longstanding limitations traditionally associated with MOSFETs. In this work, our proposed design undergoes rigorous simulations that account for process variations. The results demonstrate that our AM system closely approximates its ideal mathematical model, even with significant process variations. Furthermore, we investigate the impact of Tunnel Magnetoresistance (TMR) on the performance of our proposed AM system. Our investigations reveal that, even with a TMR as low as 100%, our design matches and often surpasses the performance of its counterparts operating with a TMR of 300%. This achievement holds profound significance from a fabrication standpoint, as fabricating MTJs with high TMR values can be intricate and costly. Overall, our novel AM system represents a significant breakthrough in emerging technologies, harnessing the unique strengths of spintronic synapses and advanced carbon nanotube transistors while robustly addressing challenges in performance and variability.

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Low-Cost and Variation-Aware Spintronic Ternary Random Number Generator

Khodayari,

Amirany,

Jafari

et al. 2023

Circuits Syst Signal Process

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A high‐capacity and nonvolatile spintronic associative memory hardware accelerator

Cited by 6 publications

References 43 publications

An efficient optical-based binary neural network hardware accelerator for harsh environments

An efficient optical-based binary neural network hardware accelerator for harsh environments

A reliable non‐volatile in‐memory computing associative memory based on spintronic neurons and synapses

Low-Cost and Variation-Aware Spintronic Ternary Random Number Generator

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