Low-power gated and buffered clock network construction

Chao, Wei-Chung; Mak, Wai-Kei

doi:10.1145/1297666.1297686

Cited by 16 publications

(19 citation statements)

References 25 publications

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“…The length of the activity pattern is 10000 for every benchmark. Previous works were proposed with loose constraint on slew or driving power supply, for instance, ≤ 20 × C g for a buffer or gate insertion in [17,16]. The work in [14] did not involve clock routing and synthesis.…”

Section: Resultsmentioning

confidence: 99%

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Clock Network Synthesis with Concurrent Gate Insertion

Chow

Sham

2011

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

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Abstract. In VLSI digital circuits, clock network plays an important role on the total performance of the chip. Clock skew and power dissipation are two major focuses of concerns in the clock network synthesis. During topology generation, the locations of buffer and gate insertion are usually not available. Despite local optimization, the global performance is limited. In this paper, a novel approach of topology generation with concurrent gate insertion is proposed. Meanwhile, a strict clock slew constraint is applied with comprehensive buffer insertion techniques. By clock gating, the switched capacitance of the clock tree is reduced, with acceptable extra cost caused in controller tree. In experimental results it is shown that our approach has good performance on the reduction of both clock skew and power dissipation.

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Section: Resultsmentioning

confidence: 99%

“…The algorithm constructed the topology in a bottom-up procedure, with the objective of switched capacitance minimization. Further on, in [17] a comprehensive technique with a recursive computation on effective switched capacitance and a solution sampling on merging segment set was discussed.…”

Section: Introductionmentioning

confidence: 99%

Clock Network Synthesis with Concurrent Gate Insertion

Chow

Sham

2011

Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation

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“…This latch is being added to the circuit such that it can boost the signals so that the clock gating is efficient. By the use of the above explained clock gating design, the normal gated clock tree can be formed as in fig 2.This design [5], as it is evitable that the area it occupies is small, but the skew is obviously added in addition to the design's skew. …”

Section: Gated Clock Treementioning

confidence: 99%

Skew Managed Global Clock Network Using Type Matching

Darling¹

2016

IJRASET

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Abstract-Clock gating has emerged as an effective low power technique these days. Various researches are being made in the optimization of this technique. While clock gating finds its applications in the clock tree synthesis, it's crucial that this additional circuitry does not include skew to the entire chip design. Also when the clock gating involves the use of all gates, (i.e.) NAND, NOR which has different timing behaviours, there is a definite possibility of an increase in skew. Therefore, in this paper a global clock tree design called type matching is proposed, wherein same type of gate at every level of clock tree is maintained, replacing even the buffers with the same type of gate buffers with the proposed mechanism. Also a comparison on the normal clock gated tree and type matched clock tree is done and proved that the clock skew minimization is achieved in type matched clock trees at the cost of clock tree area and power consumption.

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“…Recently, a comprehensive technique [31] was proposed. It is composed of a recursive computation on effective switched capacitance and a solution sampling method based on merging segment set.…”

mentioning

confidence: 99%

“…A binary clock tree is constructed in a bottom-up course. In PACTS, we apply the same slew constraint as those previous clock gating works [30], [31]. Based on the nearest-neighbor-selection (NNS) [15] binary tree topology construction, we propose a novel simultaneous gate/buffer insertion method to reduce the power.…”

mentioning

confidence: 99%

Fast Power- and Slew-Aware Gated Clock Tree Synthesis

Chow

Sham

2012

IEEE Trans. VLSI Syst.

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Abstract-Clock tree synthesis plays an important role on the total performance of chip. Gated clock tree is an effective approach to reduce the dynamic power usage. In this paper, two novel gated clock tree synthesizers, power-aware clock tree synthesizer (PACTS) and power-and slew-aware clock tree synthesizer (PSACTS), are proposed with zero skew achieved based on Elmore RC model. In PACTS, the topology of the clock tree is constructed with simultaneous buffer/gate insertion, which reduces the switched capacitance. In PSACTS, a more practical clock slew constraint is applied. Compared to previous works, clock tree synthesis is done first and followed by the insertions of clock gates. The clock slew changes a lot after the insertions of clock gates in real cases. In our work, the clock tree is constructed simultaneously with the insertions of clock gates. This ensures the limitation of the clock slew can be strictly satisfied while the limitation of the clock slew is always applied in the real design. The experimental results show that the power cost of our work is smaller and the runtime is reduced. The slew rate constraint is satisfied with a small clock skew from SPICE estimation. Generally, our work has better performance, improved efficiency and is more practical to be applied in the industry.

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Low-power gated and buffered clock network construction

Cited by 16 publications

References 25 publications

Clock Network Synthesis with Concurrent Gate Insertion

Clock Network Synthesis with Concurrent Gate Insertion

Skew Managed Global Clock Network Using Type Matching

Fast Power- and Slew-Aware Gated Clock Tree Synthesis

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