Fast Power- and Slew-Aware Gated Clock Tree Synthesis

Abstract

Abstract-Clock tree synthesis plays an important role on the total performance of chip. Gated clock tree is an effective approach to reduce the dynamic power usage. In this paper, two novel gated clock tree synthesizers, power-aware clock tree synthesizer (PACTS) and power-and slew-aware clock tree synthesizer (PSACTS), are proposed with zero skew achieved based on Elmore RC model. In PACTS, the topology of the clock tree is constructed with simultaneous buffer/gate insertion, which reduces the switched capacitance. In PSACTS, a more practical clock slew constraint is applied. Compared to previous works, clock tree synthesis is done first and followed by the insertions of clock gates. The clock slew changes a lot after the insertions of clock gates in real cases. In our work, the clock tree is constructed simultaneously with the insertions of clock gates. This ensures the limitation of the clock slew can be strictly satisfied while the limitation of the clock slew is always applied in the real design. The experimental results show that the power cost of our work is smaller and the runtime is reduced. The slew rate constraint is satisfied with a small clock skew from SPICE estimation. Generally, our work has better performance, improved efficiency and is more practical to be applied in the industry.

Low-power gated clock tree optimization for three-dimensional integrated circuits

“…Some recent works [6], [7], [8] further presented the pre-bond testing clock tree routing and TSV-obstacle-aware clock routing algorithms to construct TSV-overlap-free buffered clock trees. It has been shown that applying clock gating cells [9], [10], [11], [12], [13], [14], [15], [16] to clock network is one of the most effective methods in saving IC dynamic power and improving circuit reliability. However, none of the previous works considers clock gating cells during clock tree synthesis for 3D ICs.…”

ePlace

“…Placement performance largely impacts the downstream stages of power grid design [Wang et al 2013], clock tree synthesis [Lu et al 2012a], power optimization [Lu et al 2012b], global detail routing [Lu and Sham 2013], postlayout simulation [He et al 2012], and design variability [Zheng et al 2014]. As the technology node enters the deep nanometer scale [ITRS 2011] with billion-transistor integration, the performance of the placement engine becomes dominant on the overall quality of the design.…”

Gated low-power clock tree synthesis for 3D-ICs

“…Clock gating for 2D clock tree has been extensively studied in the past [5,11,4,8,3,10,13]. Recently with the emergence of three-dimensional circuits (3D-ICs), 3D clock design has become an active research topic.…”

“…The shutdown network in 2D clock tree is a planar Star network(one centralized control center delivering enable signals to each of the shutdown gates through one wire) and the wiring overhead is usually ignored, meaning that designers can always deliver the enable signals to wherever needed. Works in [5,11,10] insert control gate as long as the power saved by shutting down the subtree outweighs the power consumed by the gate's control network. However, the assumption that shutdown gates can be inserted at every tree node and wiring overhead of the Star network is negligible is no longer valid for 3D clock tree.…”