Low-Power Gate Driver Circuit for TFT-LCD Application

Lin, Chin‐Tarng; Tu, Chun‐Hao; Wu, Chia-En; Hung, Ching‐Wen; Gan, Kwang–Jow; Chou, Kuan-Wen

doi:10.1109/ted.2012.2186966

Cited by 40 publications

(26 citation statements)

References 16 publications

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“…Due to the mature fabrication, low cost, and compactness of the hydrogenated amorphous TFT (a-Si:H TFT), it surpasses other technologies. The amorphous silicon gate (ASG) driver circuit, however, needs a stable output waveform and lower power consumption [8][9][10]. Therefore, the dynamic characteristics, such as the rise time, fall time, ripple peak, and power, play a crucial role in determining the correct pixel data voltage.…”

Section: Introductionmentioning

confidence: 99%

Optimal design of a novel amorphous silicon gate driver circuit using a TFT-circuit-simulation-based multi-objective evolutionary algorithm

Hung

Chiang

et al. 2016

Journal of Information Display

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Optimal design of a novel amorphous silicon gate driver circuit using a TFT-circuit-simulationbased multi-objective evolutionary algorithm, Journal of Information Display, 17:2, 51-58, DOI: 10.1080/15980316.2016 A short rise time, short fall time, and small ripple are required to reduce the misoperation of pixel data voltage and to improve the stable signal processing of a driver circuit. In this study, a novel amorphous silicon gate (ASG) driver circuit consisting of 15 hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) and two capacitors was optimized using a thin-film transistor (TFT)-circuitsimulation-based multi-objective evolutionary algorithm on the unified optimization framework . The ASG circuit was optimized for the following given specifications: rise time < 0.7 µs; fall time < 0.6 µs; ripple peak < 6.5 V; clock Ctotal < 40 pf; and total TFT widths < 6000 µm. The main findings of this study show that the rise time had an 18% reduction and that the fall time, total widths, and clock Ctotal had 7, 17.5, and 9% reductions, respectively. ARTICLE HISTORY

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Section: Introductionmentioning

confidence: 99%

Optimal design of a novel amorphous silicon gate driver circuit using a TFT-circuit-simulation-based multi-objective evolutionary algorithm

Hung

Chiang

et al. 2016

Journal of Information Display

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“…By integrating scan driver with thin film transistors (TFTs) on the panel, the display systems can be cheaper and thinner [4][5][6]. However, there are some difficulties for MOTFTs to integrate the scan driver due to the considerable leakage current with the gate-source voltage as zero compared with a-Si:H TFTs or low-temperature poly-Si TFTs.…”

Section: Introductionmentioning

confidence: 99%

A low-power scan driver employing IZO TFTs including an AC–DC type output module

et al. 2015

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“…I NTEGRATED gate driver circuits on glass substrates have been developed for active-matrix liquid-crystal displays (LCDs) because this technology provides the overall compactness, mechanical reliability, and reduction in the cost of external gate driver ICs [1]- [13]. Among various thin-film transistors (TFTs), hydrogenated amorphous silicon (a-Si:H) TFTs are extensively used to manufacture the peripheral driver circuits and pixel circuits on glass substrates in active-matrix backplanes, owing to the low cost, simple process, high yield, and good uniformity over large-area substrates [9].…”

Section: Introductionmentioning

confidence: 99%

Low-Power a-Si:H Gate Driver Circuit With Threshold-Voltage-Shift Recovery and Synchronously Controlled Pull-Down Scheme

Lin

Cheng

et al. 2015

IEEE Trans. Electron Devices

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This paper presents a new low-power gate driver circuit designed by hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). An attempt is also made to reduce the power consumption resulting from the high-frequency pulldown structure, in which a pair of 0.25-Hz clock signals is used to implement a low-frequency and synchronously controlled pull-down scheme for recovering the threshold voltage shifts of a-Si:H TFTs under the negative gate-to-source voltage and decreasing the used TFTs. Measurement results indicate that the proposed gate driver circuit consumes 98.7 µW/stage, and the output waveforms are very stable without distortion when the proposed circuit is operated at 100°C for 840 h. Furthermore, the feasibility of the proposed gate driver circuit is demonstrated for the quad-extended-video-graphics-array resolution.Index Terms-Gate driver circuit, power consumption, quad-extended video graphics array (QXGA), threshold voltage shift.

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Low-Power Gate Driver Circuit for TFT-LCD Application

Cited by 40 publications

References 16 publications

Optimal design of a novel amorphous silicon gate driver circuit using a TFT-circuit-simulation-based multi-objective evolutionary algorithm

Optimal design of a novel amorphous silicon gate driver circuit using a TFT-circuit-simulation-based multi-objective evolutionary algorithm

A low-power scan driver employing IZO TFTs including an AC–DC type output module

Low-Power a-Si:H Gate Driver Circuit With Threshold-Voltage-Shift Recovery and Synchronously Controlled Pull-Down Scheme

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