In this paper, for the first time, a novel amorphous-silicon thin-film transistor gate drive circuit and its successfully improved dynamic characteristics are presented. Not only was the output ripple suppressed; the rate of threshold voltage shift was also reduced by up to 20%. About 50% power-saving was also estimated. The amorphous-silicon gate driver circuit was further fabricated, and the measured results show the high practicability of the achieved design. IntroductionThe amorphous-silicon gate (ASG) driver technology has been a key technique of late in designing gateless panels in the liquid crystal display (LCD) market [1][2][3][4][5]. It has been known that there is a major contrast between the conventional and ASG panels, as shown in Figure 1. In the conventional panel, the gate drivers are fabricated using silicon chips, and are externally bonded on the panel glass. Furthermore, in the ASG panel, the gate drivers are made of amorphous-silicon thin-film transistors (TFTs) and are internally embedded in the glass. Lower fabrication cost is the most striking strategy in the TFT-LCD market, not only for the panels for mobile phones, which can be integrated with ASGs, but also for the panels for tablets and monitors. The first advantage of the gateless TFT-LCD is the economical elimination of the external gate driver integrated circuits (ICs). This is the key factor for reducing the fabrication cost of the ASG panel. The second advantage of the gateless TFT-LCD is the improved productivity by removing the bonding process of the gate driver integrated circuits (ICs). The bonding process can be simplified. The last advantage of the gateless TFT-LCD is the achievement of a slim border and a high-resolution LCD panel due to the smaller ASG layout space beside the active area. Intrinsically, however, there are some critical issues with regard to the ASG circuit, such as high-power consumption [5], steady-state leakage current, and threshold voltage (V th ) shift after stress. The most critical issue concerns the reliability of the a-Si TFT, which directly affects the performance of the ASG circuit. In this regard, the image quality and lifetime of the LCD product are influenced. The yield rate control is also an important concern.
Optimal design of a novel amorphous silicon gate driver circuit using a TFT-circuit-simulationbased multi-objective evolutionary algorithm, Journal of Information Display, 17:2, 51-58, DOI: 10.1080/15980316.2016 A short rise time, short fall time, and small ripple are required to reduce the misoperation of pixel data voltage and to improve the stable signal processing of a driver circuit. In this study, a novel amorphous silicon gate (ASG) driver circuit consisting of 15 hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs) and two capacitors was optimized using a thin-film transistor (TFT)-circuitsimulation-based multi-objective evolutionary algorithm on the unified optimization framework . The ASG circuit was optimized for the following given specifications: rise time < 0.7 µs; fall time < 0.6 µs; ripple peak < 6.5 V; clock Ctotal < 40 pf; and total TFT widths < 6000 µm. The main findings of this study show that the rise time had an 18% reduction and that the fall time, total widths, and clock Ctotal had 7, 17.5, and 9% reductions, respectively. ARTICLE HISTORY
Mathematical models that have been employed to synthesize spatial mechanisms for rigid body guidance have been found to be too complicated to implement in practical applications, especially for four-position guidance synthesis. This paper describes simple analytical methods for synthesizing single degree-of-freedom spatial mechanisms having two independent loops for four precision positions. In addition, prescribed timing has been simultaneously considered for several spatial mechanisms.
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