Low-Power a-Si:H Gate Driver Circuit With Threshold-Voltage-Shift Recovery and Synchronously Controlled Pull-Down Scheme

Abstract

This paper presents a new low-power gate driver circuit designed by hydrogenated amorphous silicon thin-film transistors (a-Si:H TFTs). An attempt is also made to reduce the power consumption resulting from the high-frequency pulldown structure, in which a pair of 0.25-Hz clock signals is used to implement a low-frequency and synchronously controlled pull-down scheme for recovering the threshold voltage shifts of a-Si:H TFTs under the negative gate-to-source voltage and decreasing the used TFTs. Measurement results indicate that the proposed gate driver circuit consumes 98.7 µW/stage, and the output waveforms are very stable without distortion when the proposed circuit is operated at 100°C for 840 h. Furthermore, the feasibility of the proposed gate driver circuit is demonstrated for the quad-extended-video-graphics-array resolution.Index Terms-Gate driver circuit, power consumption, quad-extended video graphics array (QXGA), threshold voltage shift.

Highly reliable a‐Si:H gate driver on array with complementary double‐sided noise‐eliminating and dual voltage levels for TFT‐LCD applications

“…Especially, gate driver on array (GOA) using a-Si:H TFTs integrated on glass substrates possesses a variety of advantages, including low fabrication costs and the reductions of external driver ICs and border processes. [1][2][3][4][5][6][7][8][9][10][11] However, there are several problems for the GOA using a-Si:H TFT, such as low effect-field mobility, long-term stress degradation, and high parasitic capacitance.…”

“…Previous research built different types of noise-eliminating schemes to solve the distortion problems. [3][4][5][6][7][8][9][10][11][12][13] Figure 1 depicts the method for overcoming the stress-induced degradation issue of the gate driver. 5 The double noise-eliminating blocks (T4 to T9) and replica block (T11 to T16) take responsibility for eliminating the noise from the pre-charging node (Q node) and output node (VO node) in the first stage.…”

“…Hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (a‐Si:H TFT) has been widely applied to the pixel array and peripheral driver circuits for flat‐panel displays (FPDs) due to its low cost and high uniformity. Especially, gate driver on array (GOA) using a‐Si:H TFTs integrated on glass substrates possesses a variety of advantages, including low fabrication costs and the reductions of external driver ICs and border processes 1–11 . However, there are several problems for the GOA using a‐Si:H TFT, such as low effect‐field mobility, long‐term stress degradation, and high parasitic capacitance.…”

“…The large parasitic capacitance leads to the signal distortion generated by clock feedthrough, so that the gate driver requires additional noise‐eliminating modules to eliminate the ripple, meaning large layout area of signals line and devices. Previous research built different types of noise‐eliminating schemes to solve the distortion problems 3–13 . Figure 1 depicts the method for overcoming the stress‐induced degradation issue of the gate driver 5 .…”

Robust Gate Driver on Array Based on Amorphous IGZO Thin-Film Transistor for Large Size High-Resolution Liquid Crystal Displays

“…Small threshold voltage variation of a-IGZO TFTs induced by processes or long-term operation might result in deterioration of the circuits [12], [13]. To address these issues, many circuit designs have been proposed in the past, which, however, increase the circuit complexity and thus the layout area [14]- [17]. Moreover, very few of these designs were realized with large area manufacturing processes, and their functionalities were not verified through standard reliability tests.…”