Low power DSP engine for wireless communications

Verbauwhede, Ingrid; Touriguian, M.

doi:10.1016/s0920-5489(99)90885-1

Cited by 5 publications

(5 citation statements)

References 2 publications

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“…Ideally one would want the power efficiency of a hardwired ASIC solution while maintaining the flexibility of a programmable processor, and the design space between the hardwired ASICs and the general-purpose DSP's attracts a significant amount of research interest [85,93,77,56,78,61,57,58,63,82,69,89,48,1,52,54]. A similar trend is identified in the SIA 2001 technology roadmap that predicts "flexibility-efficiency trade-off shifting away from general purpose processing" [12].…”

Section: Application/domain-specific Processorsmentioning

confidence: 92%

“…A domain-specific approach has also been chosen to design the Lode DSP core [89]. It is a 16-bit DSP engine developed specifically for next generation wireless digital systems.…”

Section: Programmable Dspsmentioning

confidence: 99%

“…In some designs, the performance improvements obtained through parallelism can be traded with low power consumption [89,52] by using low voltage and slow clock frequency. One such DSP architecture is from Kumura et al [52].…”

Section: Programmable Dspsmentioning

confidence: 99%

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Low-Power Digital Signal Processing

Oklobdzija¹

2001

The Computer Engineering Handbook

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This thesis introduces a novel approach to programmable and low power platform design for audio signal processing, in particular hearing aids. The proposed programmable platform is a heterogeneous multi-processor architecture consisting of small and simple instruction set processors called mini-cores as well as standard DSP/CPU-cores that communicate using message passing.The work has been based on a study of the algorithm suite covering the application domain. The observation of dominant tasks for certain algorithms (FIR, IIR, correlation, etc.) that require custom computational units and special data addressing capabilities lead to the design of low power mini-cores. The algorithm suite also consisted of less demanding and/or irregular algorithms (LMS, compression) that required sub-sample rate signal processing justifying the use of a DSP/CPUcore.The thesis also contributes to the recent trend in the development of intellectual property based design methodologies. The actual mini-core designs are parameterized in word-size, memory-size, etc. and can be instantiated according to the needs of the application at hand. They are intended as low power programmable building blocks for a standard cell synthesis based design flow leading to a system-on-chip.Two mini-cores targeting FIR and IIR type of algorithms have been designed to evaluate the concept. Results obtained from the design of a prototype chip demonstrate a power consumption that is only 1.5 -1.6 times larger than commercial hardwired ASICs and more than 6 -21 times lower than current state of the art low-power DSP processors.An orthogonal but practical contribution of this thesis is the test bench implementation. A PCI-based FPGA board has been used to equip a standard desktop PC with tester facilities. The test bench proved to be a viable alternative to conventional expensive test equipment.

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Section: Application/domain-specific Processorsmentioning

confidence: 92%

“…A domain-specific approach has also been chosen to design the Lode DSP core [89]. It is a 16-bit DSP engine developed specifically for next generation wireless digital systems.…”

Section: Programmable Dspsmentioning

confidence: 99%

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Low-Power Digital Signal Processing

Oklobdzija¹

2001

The Computer Engineering Handbook

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“…Some special function blocks also influence the performance of application-specific DSPs. Notably, special functional blocks such as square-distance-and-accumulate for vector quantization, add-compare-select for the Viterbi algorithm, and the Galois field operation for forward errorcontrol coding are provided in certain DSPs for baseband operations [4,5,6,7,8]. For example, Lucent's DSP 1618 performs Viterbi decoding using a coprocessor, which supports various decoding modes with control registers [5].…”

Section: Introductionmentioning

confidence: 99%

Low-Power Embedded DSP Core for Communication Systems

Tsao

Chen

Tan

et al. 2003

EURASIP J. Adv. Signal Process.

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This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35 m SPQM and 0.25 m 1P5M library. The equivalent gate count of the core area without memory is approximately 50 k. Moreover, the maximum operating frequency of a version is 100 MHz (0.35 m) and 140 MHz (0.25 m).

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“…DSP Group has its Pine [3] and Oak [4] cores, Clarkspur Design the CD2450 [5], and TCSI the Lode core [6]. All of these have several licensees.…”

Section: Traditional Dsp Coresmentioning

confidence: 99%

A new generation of parameterized and extensible DSP cores

Nurmi¹,

Takala²

1997 IEEE Workshop on Signal Processing Systems. SiPS 97 Design and Implementation Formerly VLSI Signal Processing

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Traditional DSP cores based on off-the-shelf processors do not provide any possibilities to configure the core itself. This has been addressed by licensable, customizable cores. This paper introduces a new generation of parameterized and extensible DSP cores. The VSDSP core features can be tailored to the application by changing the parameters. Furthermore, there are several extension mechanisms incorporated to the architecture, enabling the exploration of hardware-software tradeoffs in core based ASIC design.

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Low power DSP engine for wireless communications

Cited by 5 publications

References 2 publications

Low-Power Digital Signal Processing

Low-Power Digital Signal Processing

Low-Power Embedded DSP Core for Communication Systems

A new generation of parameterized and extensible DSP cores

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