A new generation of parameterized and extensible DSP cores

Nurmi, Jari; Takala, Jarmo

doi:10.1109/sips.1997.626254

Cited by 8 publications

(2 citation statements)

References 7 publications

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“…Recently, a more flexible DSP core has been proposed, namely, the so-called parameterized DSP core [20]. The parameterized DSP core is parameterized using several independent parameters.…”

Section: Optional Special Functional Blocks and Parametersmentioning

confidence: 99%

Low-Power Embedded DSP Core for Communication Systems

Tsao

Chen

Tan

et al. 2003

EURASIP J. Adv. Signal Process.

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This paper proposes a parameterized digital signal processor (DSP) core for an embedded digital signal processing system designed to achieve demodulation/synchronization with better performance and flexibility. The features of this DSP core include parameterized data path, dual MAC unit, subword MAC, and optional function-specific blocks for accelerating communication system modulation operations. This DSP core also has a low-power structure, which includes the gray-code addressing mode, pipeline sharing, and advanced hardware looping. Users can select the parameters and special functional blocks based on the character of their applications and then generating a DSP core. The DSP core has been implemented via a cell-based design method using a synthesizable Verilog code with TSMC 0.35 m SPQM and 0.25 m 1P5M library. The equivalent gate count of the core area without memory is approximately 50 k. Moreover, the maximum operating frequency of a version is 100 MHz (0.35 m) and 140 MHz (0.25 m).

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“…Recently, a more flexible DSP core has been proposed, namely, the so-called parameterized DSP core [20]. The parameterized DSP core is parameterized using several independent parameters.…”

Section: Optional Special Functional Blocks and Parametersmentioning

confidence: 99%

Low-Power Embedded DSP Core for Communication Systems

Tsao

Chen

Tan

et al. 2003

EURASIP J. Adv. Signal Process.

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“…The commercial partner of this project addressed these limitations in a second-generation core called VS-DSP. 9 While this core retains the original's level of parameterization and extensibility, its more orthogonal register set and larger selection of branch conditions make programming easier.…”

Section: Application Examplementioning

confidence: 99%

A flexible DSP core for embedded systems

Kuulusa

Nurmi²,

Takala³

et al. 1997

IEEE Des. Test. Comput.

Self Cite

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for high-volume application-specific integrated circuit (ASIC) design relies on the use of programmable digital signal processing cores. Combining these dedicated, highperformance DSP engines with data and program memories and a selected set of peripherals yields a highly integrated system on a chip. Rapidly evolving silicon technologies and improving design tools are the key enablers of this approach, allowing system engineers to pack impressive amounts of functionality into a system within a reasonable development time. According to an embedded-processor market survey, 1 more than two thirds of high-volume embedded systems will be based on specialized DSP cores by the end of this decade.This approach offers many advantages. Unlike conventional methods, DSP-corebased ASIC design combines the benefits of a standard off-the-shelf DSP and optimized custom hardware. As a direct result of higher integration, it reduces unit cost, an increasingly important issue in sensitive market areas such as telecommunications and personal computing. Equally important are the improved reliability and impact on time to market of the core approach. The shrinking life span of DSP-based products forces very tight schedules that leave little time for redesign. As software content in modern signal processing applications increases, system complexity typically becomes very high. To realize target applications on schedule, sys-tem engineers must exploit the benefits of DSP cores-programmability, software libraries, and development tools-as fully as possible.Because software functions alone are not sufficient for many applications, a wide range of peripherals is available for corebased systems. In addition to essential RAM and ROM, core-based designs can include special types of memories such as FIFO, multiport, and Flash. Also available are highspeed serial buses (UART, I2C, USB), dedicated bus controllers (PCI, SCSI), A/D and D/A converters, and other special I/Os to interface the system with the off-chip world. 2 Other examples of the most common peripheral circuitry are timers, DMA controllers, and miscellaneous analog circuitry.Much larger and more complex functional entities, also called cores, are available for use as embedded on-chip peripherals. The broad diversity of these cores ranges from RISC microprocessors to dedicated discrete cosine transform (DCT) engines. 3 Moreover, system engineers can improve system performance significantly by designing a block of custom hardware outside the DSP core to implement special functionality for the application at hand.A number of issues affect the selection of a DSP core for an ASIC design. From the fabrication point of view, the alternatives are foundry-captive and licensable cores. 4 Most foundry-captive cores are derived from popular off-the-shelf counterparts and provid-

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High-level parameterizable area estimation modeling for ASIC designs

Eerola

Nurmi

2014

Integration

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A new generation of parameterized and extensible DSP cores

Cited by 8 publications

References 7 publications

Low-Power Embedded DSP Core for Communication Systems

Low-Power Embedded DSP Core for Communication Systems

A flexible DSP core for embedded systems

High-level parameterizable area estimation modeling for ASIC designs

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