Low power design of FSMs by state assignment and disabling self-loops

Koegst, M.; Franke, G.; Rulke, S.; Feske, Klaus

doi:10.1109/eurmic.1997.617303

Cited by 4 publications

(5 citation statements)

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“…Due to space limitations, and since there are numerous papers discussing these topics (e.g., see [1,3,9,10,11,13,18,25,29,30,31] and the references therein) we omit a discussion of the work on reducing energy complexity at these levels in the paper. In addition, a considerable amount of work has been done in reducing energy at various levels of the networking protocol stack.…”

Section: Related Workmentioning

confidence: 99%

Towards understanding algorithmic factors affecting energy consumption

Jain

Molnár

Ramzan

2005

Proceedings of the 2005 Joint Workshop on Foundations of Mobile Computing

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Mobile devices consider energy to be a limiting resource. Over the past decade significant research has gone into how one can reduce energy consumption at the hardware level, network protocol level, operating system level, and compiler level. In almost all algorithm analysis, a single resource such as time or communication is often taken as a proxy for energy. We address this problem by defining an algorithmic model for energy, designing algorithm variants that reduce energy cost in this model, and then performing preliminary experiments to test the model.Our starting point is an algorithmic energy model inspired by work from the compilers community [26]. Augmenting and simplifying this model motivates the need to consider an algorithm's "switching" complexity; this measure captures the extent to which one switches between different functional units during execution. We carry out preliminary experiments on the Itsy pocket computer, which contains a StrongARM SA-1100 processor running Linux, to compare "high-switch" versions of bubble sort and other algorithms to optimized "low-switch" versions. Our preliminary results show that switching does not appear to affect energy consumption at the algorithmic level.We then look at a factor that does not appear to have been studied, namely the cost of generating (pseudo)random bits. Derandomization is a goal in cryptography and complexity theory. To our knowledge the energy cost of randomness itself has not been studied. Nonetheless, many mobile protocols and algorithms might utilize randomness, for example to handle contention resolution, generate cryptographic keys, or to accomplish efficient sorting. We consider three common mechanisms for generating randomness: the standard C library random number generator, and the Linux /dev/random, and /dev/urandom generators. We perform tests that compare the energy consumed by these generators compared to the cost of performing basic arithmetic Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. DIALM-POMC'05, September 2, 2005, Cologne, Germany. Copyright 2005 ACM 1-59593-092-2/05/0009 ...$5.00.instructions. We use Quicksort as an example of a classic basic application-level algorithm to understand the energy cost of randomness, and compare the energy consumed by randomized Quicksort to standard Quicksort. Our preliminary results show that generating randomness does in fact incur a significant energy cost, and /dev/random is the most expensive of the three mechanisms.We conclude that understanding energy consumption at the algorithmic level is an important but overlooked area of investigation, and discuss the implications of our results. We end with directions for for further w...

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Section: Related Workmentioning

confidence: 99%

Towards understanding algorithmic factors affecting energy consumption

Jain

Molnár

Ramzan

2005

Proceedings of the 2005 Joint Workshop on Foundations of Mobile Computing

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“…In the synthesis of synchronous controllers, solutions proposed for reducing power are being offered at the logic level: clock logic control (gated-clock) [4,5], Flip-Flops working at the two edges of the clock transition [6,7], decomposition [8], state assignment [9] and logic minimization [10]. In a digital system, the sequential stage is the main contributor to power dissipation.…”

Section: Introductionmentioning

confidence: 99%

Synthesis of Low-Power Synchronous Controllers using FPGA Implementation

Oliveira

Salazar

Romano

2008

2008 4th Southern Conference on Programmable Logic

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Today, a number of digital systems are described by an architecture consisting of a network of synchronous controllers and datapaths. These are battery-fed and may be implemented in VLSI technology and/or FPGAs (Field Programmable Gate Array). Since the batteries must have long life, reduction of energy consumption is the most important task in the design of such systems. In order to reduce dissipated power, a number of strategies have been suggested in the literature for both controllers and datapaths. In this article we suggest an approach that applies a new strategy for the synthesis of the lowconsumption synchronous controllers. Our method synthesizes synchronous controllers that work at the two transition edges of clock signals, but only uses flip-flops that work at a single clock edge.

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“…For example Koegst et al [8] use gated clocks in FSM designs to disable the state transition of so called self-loops.…”

Section: Clock Controlmentioning

confidence: 99%

Design techniques for low-power systems

Havinga

Smit

2000

Journal of Systems Architecture

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Portable products are being used increasingly. Because these systems are battery powered, reducing power consumption is vital. In this report we give the properties of low power design and techniques to exploit them on the architecture of the system. We focus on: minimizing capacitance, avoiding unnecessary and wasteful activity, and reducing voltage and frequency. We review energy reduction techniques in the architecture and design of a hand-held computer and the wireless communication system, including error control, system decomposition, communication and MAC protocols, and low power short range networks.Keywords: low power, system architecture, mobile computing, wireless communication. IntroductionThe requirement of portability of hand-held computers and portable devices places severe restrictions on size and power consumption. Even though battery technology is improving continuously and processors and displays are rapidly improving in terms of power consumption, battery life and battery weight are issues that will have a marked influence on how hand-held computers can be used. These devices often require real-time processing capabilities, and thus demand high throughput. Power consumption is becoming the limiting factor in the amount of functionality that can be placed in these devices. More extensive and continuous use of network services will only aggravate this problem since communication consumes relatively much energy. Research is needed to provide intelligent policies for careful management of the power consumption while still providing the appearance of continuous connections to system services and applications. The advance of technologyOver the past two decades the semiconductor technology has been continuously improved and has lead to ever smaller dimensions of transistors, higher packaging density, faster circuits, and lower power dissipation. The trend is expected to continue beyond the year 2000. Over the past five years, feature sizes have dropped from about f=0.8µ to about f=0.35µ. Semiconductor Industry Associates (SIA) have developed a road map for the next few years (see figure 1). It is expected that a feature size of f=0.1µ will be reached in 2007 within the context of our current CMOS technology. Such advances provide an effective area increase of about an order of magnitude. To avoid the effect of high electric fields which would be present in very small devices, and to avoid the overheating of the devices, power supply must be scaled down. The power supply voltage is expected to be as low as 1.2 V in 2007.This rapid advance in technology can be used for several goals. It can be used to increase performance, to add functionality, but also to reduce energy consumption. The current trend is to focus on high performance processors as this is the area in which a semiconductor vendor can enhance its status [5]. Therefore, the architecture of a general purpose processor is most 2 widely studied, and optimizations for processor performance is the main goal. The advance in technology ha...

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Low power design of FSMs by state assignment and disabling self-loops

Cited by 4 publications

References 18 publications

Towards understanding algorithmic factors affecting energy consumption

Towards understanding algorithmic factors affecting energy consumption

Synthesis of Low-Power Synchronous Controllers using FPGA Implementation

Design techniques for low-power systems

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