Synthesis of Low-Power Synchronous Controllers using FPGA Implementation

Abstract

Today, a number of digital systems are described by an architecture consisting of a network of synchronous controllers and datapaths. These are battery-fed and may be implemented in VLSI technology and/or FPGAs (Field Programmable Gate Array). Since the batteries must have long life, reduction of energy consumption is the most important task in the design of such systems. In order to reduce dissipated power, a number of strategies have been suggested in the literature for both controllers and datapaths. In this article we suggest an approach that applies a new strategy for the synthesis of the lowconsumption synchronous controllers. Our method synthesizes synchronous controllers that work at the two transition edges of clock signals, but only uses flip-flops that work at a single clock edge.

Synthesis of Low-Power Synchronous Digital Systems Operating in Double-Edge of the Clock

“…Oliveira et al [8] proposed a state assignment style of FSMs based on a partition of the state transitions, which reduces by half the activity of the clock signal (state memory partitioned -SM_partition style). The state memory of the FSMs uses only SET-FFs, operating in both transitions of the clock signal (double-edge triggered synchronous FSMs).…”

“…The great advantage of this method is that it synthesizes synchronous FSMs (DET-FSM) using only SET-FF's. Some previous works found in literature [8], [17] are limited to FSMs, but most applications involve also data-paths.…”

“…Once considering the states assignment style for the synthesis of controller proposed in [8], [17], it is used just SET-FFs. It is also introduced a specification called "operations transition graph" (OTG) to generate data-paths that operates on both edges of the clock signal, but using only conventional components, such as single-edge triggered registers (counters).…”