Low-power and high-throughput hardware design for the 3D-HEVC depth intra skip

Afonso, Vladimir; Susin, Altamiro; Audibert, Luan; Saldanha, Mário; Conceição, Ruhan; Porto, Marcelo; Agostini, Luciano

doi:10.1109/iscas.2017.8050463

Cited by 7 publications

(1 citation statement)

References 3 publications

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“…A DMM-4 encoder architecture was designed in [10] and a DMM-1 encoder architecture was designed in [11]. Afonso et al [12] designed an encoder architecture for DIS. At the best of our knowledge, this is the first work presenting a decoding architecture for these new depth maps coding tools.…”

Section: Introductionmentioning

confidence: 99%

High Efficient Architecture for 3D-HEVC DMM-1 Decoder Targeting 1080p Videos

Sanchez

Agostini

Marcon

2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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This paper presents an efficient hardware design for the Depth Modeling Mode 1 (DMM-1) decoder of the 3D-High Efficiency Video Coding (3D-HEVC). The designed architecture uses a lossless wedgelet memory compression technique to reduce the used memory, and a well-balanced parallelism level to allow the desired throughput at the minimum possible power consumption and area usage. The architecture was synthesized for the 65nm ST standard cells technology, using 4,047 gates and consuming 0.95mW. It is capable of processing 1080p videos at 30 frames per second, decoding all allowed block sizes and wedgelets patterns. Besides, the proposed architecture saves 10.7% of area and 29.1% of power when compared with a version without memory compression. At the best of the author's knowledge, this is the first work with a dedicated hardware design targeting the DMM-1 decoder.

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Section: Introductionmentioning

confidence: 99%

High Efficient Architecture for 3D-HEVC DMM-1 Decoder Targeting 1080p Videos

Sanchez

Agostini

Marcon

2018

2018 IEEE International Symposium on Circuits and Systems (ISCAS)

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Hardware and coding efficiency assessment of 3D-HEVC DIS tool using alternative similarity criteria

Borges

Perleberg

Afonso

et al. 2021

Analog Integr Circ Sig Process

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3D-HEVC is the state-of-the-art standard to compress three-dimensional videos. One of the 3D-HEVC novel tools is the DIS tool, which is used to efficiently compress smooth and homogeneous areas of depth maps by using four different prediction modes. The decision of which DIS mode will be used is done through the SVDC similarity criterion in the DIS original definition. This article proposes the substitution of the complex SVDC criterion for simpler and more hardware friendly criteria as SATD, SSE, and SAD. These alternative criteria were evaluated in terms of encoding efficiency and hardware impacts in comparison with the SVDC. Dedicated DIS hardware were designed using each one of each criterion and these designs were described in VHDL and synthesized for TSMC 40 nm. The best results were found with SAD criteria, with losses of only 0.2% in coding efficiency and with expressive gains of more than 50 times in power and more than 35 times in area, when compared with SVDC. The reached results showed that the use of a simpler similarity criterion is an important alternative to be used in DIS tool, mainly if an efficient hardware design is required.

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