High Efficient Architecture for 3D-HEVC DMM-1 Decoder Targeting 1080p Videos

Abstract

This paper presents an efficient hardware design for the Depth Modeling Mode 1 (DMM-1) decoder of the 3D-High Efficiency Video Coding (3D-HEVC). The designed architecture uses a lossless wedgelet memory compression technique to reduce the used memory, and a well-balanced parallelism level to allow the desired throughput at the minimum possible power consumption and area usage. The architecture was synthesized for the 65nm ST standard cells technology, using 4,047 gates and consuming 0.95mW. It is capable of processing 1080p videos at 30 frames per second, decoding all allowed block sizes and wedgelets patterns. Besides, the proposed architecture saves 10.7% of area and 29.1% of power when compared with a version without memory compression. At the best of the author's knowledge, this is the first work with a dedicated hardware design targeting the DMM-1 decoder.

Low Area Reconfigurable Architecture for 3D-HEVC DMMs Decoder Targeting 1080p Videos

“…One of the major problems in the DMM-1 hardware design relates to the memory for storing its wedgelets [13]. Some works already proposed solutions for better storage of DMM-1 patterns such as [9], [13], and [14]. However, [9] and [14] can only be applied to the encoder side since they reduce the number of possible wedgelets.…”

“…Some works already proposed solutions for better storage of DMM-1 patterns such as [9], [13], and [14]. However, [9] and [14] can only be applied to the encoder side since they reduce the number of possible wedgelets.…”

“…In our previous work [13], First Bit and Change (FB&C) algorithm was proposed for better storage of DMM-1 patterns with the possibility to be used in both encoder and decoder, as it allows the obtaining all wedgelets patterns. Therefore, we have chosen this algorithm for integration with the designed decoder (as done in our previous work [9]).…”

“…Currently exists only a superficial exploration of dedicated hardware for depth maps coding, which is expected since 3D-HEVC is a relatively new extension. In our previous work [9], we proposed a hardware architecture for DMM-1 decoding in 3D-HEVC based on a lossless compression technique for wedgelet memory. The DMM-1 decoder is capable of processing 1080p videos at 30 frames per second while minimizing power consumption and memory requirements.…”

“…In this work, we present a reconfigurable DMMs decoding hardware design based on our previous work [9], which only implements DMM-1. Since DMM-1 and DMM-4 contain several common operations in decoding, the main contribution of our reconfigurable architecture is sharing hardware resources between modes, thus being capable of using a low area and low power design.…”