Low Area Reconfigurable Architecture for 3D-HEVC DMMs Decoder Targeting 1080p Videos

Abstract

The 3D High Efficiency Video Coding (3D-HEVC) needs specialized tools, such as the Depth Modeling Mode (DMM), for dealing with texture and depth map information. This work proposes a low area reconfigurable hardware for sharing a DMM-1 and DMM-4 decoding implementation. When synthesizing for a 65nm ST technology, the designed architecture uses only 5,165 gates and dissipates 1.57 mW, considering the frequency to decode the worst-case scenario. Compared to the state-of-the-art, it is notable that our proposal requires only a few extra hardware to enable a DMM-1 and DMM-4 sharing architecture.