Low power and high speed row and column bypass multiplier

Srinivas, K.; Aneesh, Y. Mohammed

doi:10.1109/iccic.2014.7238492

Cited by 4 publications

(3 citation statements)

References 5 publications

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“…Multiple adders have been used to carry out the addition of partial products to get the final product according to Eqs. (8)(9)(10)(11). In single iteration, the adder can take only two inputs.…”

Section: Addersmentioning

confidence: 99%

“…In [10], a re-configurable digit-serial multiplier is proposed which used clock gating for power optimization but this work does not optimize the resource consumption of FPGA. A two-dimensional bypassing technique is used in [11] to design the multiplier, and the article focused on optimization of power consumption and delay, whereas the proposed approach presented in this article optimizes the resource consumption of FPGA. In [12], a multiplexer-based 8-bit multiplier is presented with 50 MHz frequency, whereas the proposed architecture achieves 320 MHz frequency for 16-bit multiplication.…”

Section: Introductionmentioning

confidence: 99%

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An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm

et al. 2019

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A unique design for an optimized N-bit multiplier is proposed and implemented which utilizes a modified divide-andconquer technique. The conventional technique requires four N/2-bit multipliers to perform N-bit multiplication, whereas the proposed design uses only one multiplier module in hardware to perform the functionality of four modules. It uses Dadda algorithm in its multiplier module. It has been implemented using Verilog HDL, and a good accuracy of results was observed in simulations which effectively verify its functionality. Design was also synthesized on various FPGAs including Spartan 3E, Virtex-5 and Virtex-7. Performance summary, after place and route, showed that the proposed approach significantly reduces hardware utilization. Furthermore, the proposed design is almost 75% more efficient in terms of resources utilization and operating frequency as compared to the conventional design.

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Section: Addersmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An area-optimized N-bit multiplication technique using N/2-bit multiplication algorithm

et al. 2019

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“…Since signed and unsigned multiplication operation is performed by the same multiplier unit the required hardware and the chip area reduces and this in turn reduces power dissipation and cost of a system. Srinivas K.B [10] et al described a bypassing logic will reduce Dynamic power dissipation as well as signal propagation delay. The demand for electronic portable devices is gaining more attention in recent decades.…”

Section: Introductionmentioning

confidence: 99%

A Modified Architecture for Radix-4 Booth Multiplier with Adaptive Hold Logic

Suvarna¹,

Rajesh²,

Radhu³

2016

ijsrtm

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High speed digital multipliers are most efficiently used in many applications such as Fourier transform, discrete cosine transforms, and digital filtering. The throughput of the multipliers is based on speed of the multiplier, and then the entire performance of the circuit depends on it. The pMOS transistor in negative bias cause negative bias temperature instability (NBTI), which increases the threshold voltage of the transistor and reduces the multiplier speed. Similarly, the nMOS transistor in positive bias cause positive bias temperature instability (PBTI).These effects reduce the transistor speed and the system may fail due to timing violations. So here a new multiplier was designed with novel adaptive hold logic (AHL) using Radix-4 Modified Booth Multiplier. By using Radix-4 Modified Booth Encoding (MBE), we can reduce the number of partial products by half. Modified booth multiplier helps to provide higher throughput with low power consumption. This can adjust the AHL circuit to reduce the performance degradation. The expected result will be reduce threshold voltage, increase throughput and speed and also reduce power. This modified multiplier design is coded by Verilog and simulated using Xilinx ISE 12.1 and implemented in Spartan 3E FPGA kit.

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