2013
DOI: 10.1142/s021812661350062x
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Low Power and High Performance Single-Ended Sense Amplifier

Abstract: This paper presents a new power efficient single ended sense amplifier (SA). The proposed circuit is based on the direct current voltage conversion technique. It has been simulated using Microwind3 and DSCH3 tools (advanced BSIM 4 level) for 90 nm CMOS technology in terms of power consumption, sense time and results were compared to other circuits. The proposed SA circuit consumes more than 50% less power and gives 90% faster sensing speed compared to other circuits. The lower power consumption is due to lower… Show more

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Cited by 5 publications
(4 citation statements)
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“…3) and observed that correct logic is obtained at two nodes for all the inputs combinations except 101 and 110 case. Since, in 4-bit series adder circuit, carry signal of first adder acts as input for the second adder and so on, it is observed that due to weak controlling signal at the gate of transistor N3, CARRY output degraded from 0.698 V to 0 V which can be restored by using sense amplifier (SA) [12] or using low threshold voltage transistors N3 and N4. SA restores the output voltage swing and provides the appropriate output current to drive the fan-out capacitances whereas reduction in threshold voltages of the PTL transistors improves performance without increase in leakage current as in static CMOS logic.…”
Section: Architecture and Layout Of The Proposed Circuitmentioning
confidence: 99%
“…3) and observed that correct logic is obtained at two nodes for all the inputs combinations except 101 and 110 case. Since, in 4-bit series adder circuit, carry signal of first adder acts as input for the second adder and so on, it is observed that due to weak controlling signal at the gate of transistor N3, CARRY output degraded from 0.698 V to 0 V which can be restored by using sense amplifier (SA) [12] or using low threshold voltage transistors N3 and N4. SA restores the output voltage swing and provides the appropriate output current to drive the fan-out capacitances whereas reduction in threshold voltages of the PTL transistors improves performance without increase in leakage current as in static CMOS logic.…”
Section: Architecture and Layout Of The Proposed Circuitmentioning
confidence: 99%
“…To address these concerns, we have designed new architectures for these circuits to reduce the power consumptions. The detail about these circuits is available in our published work [108,109].…”
Section: Proposed Decoder Circuits and Sense Amplifiermentioning
confidence: 99%
“…As we know most of the current will be dissipated in the SRAM cell by sense amplifier. To address this issue we have also designed a single-ended sense amplifier [109]. The proposed SA (sense amplifier) reduces the power consumption by controlling the leakage current during evaluation/precharge mode.…”
Section: Proposed Decoder Circuits and Sense Amplifiermentioning
confidence: 99%
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