Low Power and High Performance Clock Delayed Domino Logic using Saturated Keeper

Amirabadi, Amir; Chehelcheraghi, A.; Rasouli, S.H.; Seyedi, A.S.; Afzai-Kusha, A.

doi:10.1109/iscas.2006.1693299

Cited by 5 publications

(2 citation statements)

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“…However, dual keeper structures either contribute heavier loading on the output nodes of dynamic gates or increase the circuit complexity. An alternative approach is to apply a single keeper with two conductivity values, such as the saturated keeper [13] and the four-phase keeper [14]. These keepers employ the threshold voltage V T dropping properties by propagating supply voltage level V DD /ground level (GND) through the nMOS/pMOS to partially turn on the keeper in the early evaluation phase.…”

Section: Weak Contention At the Early Evaluation Phasementioning

confidence: 99%

“…A further complex working phase is needed to generate the required V T or V DD − V T level and burden the clock signal, e.g., the four-phase keeper [14] requires two phases to generate V T to drive keeper. The saturated keeper [13] is simple, but it fails to generate the required (V DD − V T ) voltage level to drive keeper when evaluating logic 0 on the dynamic node in the previous evaluation phase. It then works as a contention-free keeper in such a situation, in contradiction of its original design concept.…”

Section: Weak Contention At the Early Evaluation Phasementioning

confidence: 99%

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Adaptive Pseudo Dual Keeper for Wide Fan-In Dynamic Circuits

Huang

Wang

2011

IEEE Trans. Circuits Syst. II

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This brief presents a novel keeper technique for high-performance and high-noise-immunity wide fan-in dynamic circuits. Two major innovations are proposed, i.e., the adaptive pseudo dual keeper technique, which can either significantly reduce evaluation contention or maximize immediate noise immunity through a simple single keeper structure, and the diodeconnected self-biasing circuit to minimize the static current of the adaptive pseudo dual keeper. Both these original design concepts help to achieve higher performance and lower power consumption while maintaining the high noise immunity. Several wide fan-in dynamic gates were designed using UMC 90-nm 1-V technology. Our simulation results demonstrate that using the proposed keeper technique, the 32-bit OR gate and multiplexer can achieve delay reductions of at least 22% and 17.7%, respectively, for the same unity-gain direct-current noise (UGDN)-immunity requirement, as compared with conventional keeper techniques. Meanwhile, power dissipation is reduced by up to 55.3% due to the simple keeper structure and contention reduction. The simulations also show that circuits with the proposed keeper show small variations in delay and power consumption over a wide range of noiseimmunity requirements, e.g., they vary by only 2.1% and 3.2% for a 32-bit multiplexer with 0.24-to 0.32-V UGDN levels.

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Section: Weak Contention At the Early Evaluation Phasementioning

confidence: 99%

Section: Weak Contention At the Early Evaluation Phasementioning

confidence: 99%