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This brief presents a novel keeper technique for high-performance and high-noise-immunity wide fan-in dynamic circuits. Two major innovations are proposed, i.e., the adaptive pseudo dual keeper technique, which can either significantly reduce evaluation contention or maximize immediate noise immunity through a simple single keeper structure, and the diodeconnected self-biasing circuit to minimize the static current of the adaptive pseudo dual keeper. Both these original design concepts help to achieve higher performance and lower power consumption while maintaining the high noise immunity. Several wide fan-in dynamic gates were designed using UMC 90-nm 1-V technology. Our simulation results demonstrate that using the proposed keeper technique, the 32-bit OR gate and multiplexer can achieve delay reductions of at least 22% and 17.7%, respectively, for the same unity-gain direct-current noise (UGDN)-immunity requirement, as compared with conventional keeper techniques. Meanwhile, power dissipation is reduced by up to 55.3% due to the simple keeper structure and contention reduction. The simulations also show that circuits with the proposed keeper show small variations in delay and power consumption over a wide range of noiseimmunity requirements, e.g., they vary by only 2.1% and 3.2% for a 32-bit multiplexer with 0.24-to 0.32-V UGDN levels.

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