Keeper Effect on Nano Scale Silicon Domino Logic Transistors

Pandey, Amit Kumar; Gupta, Tarun Kumar; Gupta, Abhinav; Pandey, Digvijay

doi:10.1007/s12633-021-01424-6

Cited by 6 publications

(2 citation statements)

References 26 publications

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“…Modified Keeper Circuit: Figure 1 shows the modified keeper circuit, which contains two keeper transistors MK1 and MK2. The gate terminal of MK1 transistor is operated by the output of inverter, whereas the gate terminal of MK2 transistor is driven by dynamic node of the circuit [4]. The keeper transistor MK1, which is controlled by the inverted output, helps in maintaining the voltage of dynamic node and the keeper transistor MK2 helps to improve the noise immunity and the speed of the circuit.…”

Section: Introductionmentioning

confidence: 99%

Dual Threshold Voltage Pseudo Domino Logic - Based Buffer with Reduced Power

Verma

Kumar

Deo

2022

IOP Conf. Ser.: Mater. Sci. Eng.

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In this paper, a new technique of power reduction in pseudo domino logic-based buffer is proposed with dual threshold voltage. The proposed method employs the dual threshold voltage technique to reduce the power. During the precharge stage, we have used the high threshold voltage transistor in the non-critical path of the circuit, to reduce the leakage current due to which the average power dissipation is minimized. In critical path, low threshold voltage transistors are used. The low threshold voltage transistors are used in evaluation stage, for the performance enhancement of the circuit. Keeper circuit is used with two PMOS transistor which helps in maintaining voltage of dynamic node and improves the noise immunity and speed of the circuit. Also, a NMOS transistor, which is operated by the dynamic node is used which minimizes the leakage by creating a stacking impact. In addition, the clock inverter is enabled via low voltage NMOS which significantly reduces the current in the inverter due to direct connection between the supply voltage (Vdd) to ground.

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Section: Introductionmentioning

confidence: 99%

Dual Threshold Voltage Pseudo Domino Logic - Based Buffer with Reduced Power

Verma

Kumar

Deo

2022

IOP Conf. Ser.: Mater. Sci. Eng.

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“…Garg et al have proposed using the stack effect to reduce the noise effect and leakage currents, however at the cost of a delay penalty due to the addition of an inverter between the dynamic node and the output node [55]. In [56], a delay network containing an odd number of inverters was used to control the keeper. Finally, in [57], a floating-gate MOS transistor whose equivalent resistance depends on the number of the activated inputs was adopted.…”

mentioning

confidence: 99%

A Charge-Accumulation Based High-Performance CMOS Circuit

Sharroush

2022

Port-Said Engineering Research Journal

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There is no doubt that complementary metal-oxide semiconductor (CMOS) circuits with wide fan-in suffers from degraded performance. In this paper, a circuit that depends on charge accumulation is proposed as an alternative to conventional CMOS design. The proposed scheme is investigated quantitatively and verified by simulation using predictive technology model (PTM) of the 45 nm CMOS technology with a power-supply voltage, VDD, equal to 1 V. Although the proposed scheme suffers from more sensitivity to process variations compared to static CMOS, the comparative analysis and simulation results confirm the superiority of the proposed scheme from the points of view of speed, area, power consumption, and unity-noise gain. It is verified that the proposed scheme has a smaller area, power consumption, and delay compared to the conventional CMOS design when the number of inputs, n, exceeds four, two, and three, respectively. The impacts of process variations, component mismatches, and technology scaling are also investigated. The speed advantage gained from the proposed scheme is expected to be more obvious when operating in the subthreshold region. A figure of merit including the unity-noise gain, area, power consumption, and time delay is defined and the proposed scheme showed superior performance compared to the conventional CMOS logic when n exceeds four. Finally, the proposed scheme was compared with various previous schemes.

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