Low Power 16 Phase Ring Oscillator and PLL for Use in sub-ns Time Synchronization over Ethernet

Buhr, Simon; Kreissig, Martin; Ellinger, Frank

doi:10.1109/icecs.2018.8617944

Cited by 7 publications

(2 citation statements)

References 5 publications

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“…This clock is also used to clock the digital control block of the equaliser. The CDR is realised fully digital as in [17] by selecting one clock phase of a 16 clock ring oscillator [18].…”

Section: Automatic Control Of the Equaliser Parametersmentioning

confidence: 99%

Low power analogue equaliser with adaptive digital tuning for fast ethernet

Buhr

Kreissig

et al. 2020

IET Circuits, Devices & Systems

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This work presents an analogue equaliser with digital tuning. It compensates the losses introduced by up to 120 m long category 5 unshielded twisted pair cables and baseline wander (BLW). The equaliser is designed for Fast Ethernet with a symbol rate of 125 MHz. A g m-C filter, based on three first-order high pass filters, is used to compensate the cable loss. To minimise power consumption, three operational transconductance amplifiers (OTAs) are merged into a novel multi-input OTA structure. Additionally, a robust digital control logic is presented to automatically adjust the parameters of the equaliser for different cable lengths. A fast settling time below 250 µs is demonstrated for different scenarios. The equaliser is fabricated as part of a Fast Ethernet PHY chip in a 180 nm CMOS technology of GLOBALFOUNDRIES. Measurement results demonstrate error-free data transmission (bit error rate below 10 −12) for cable lengths up to 120 m. The power consumption of the analogue equaliser ranges from 2.3 mW (short cable) to 6.5 mW (120 m cable). To the best of the authors' knowledge, this is the lowest power consumption of an analogue equaliser for Fast Ethernet, supporting additional BLW and flat loss compensation reported to date.

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“…This clock is also used to clock the digital control block of the equaliser. The CDR is realised fully digital as in [17] by selecting one clock phase of a 16 clock ring oscillator [18].…”

Section: Automatic Control Of the Equaliser Parametersmentioning

confidence: 99%

Low power analogue equaliser with adaptive digital tuning for fast ethernet

Buhr

Kreissig

et al. 2020

IET Circuits, Devices & Systems

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“…When such extremely low noise levels are not mandatory, integrated ring oscillators can prove their usage. In terms of area usage, ring oscillators can be as small as a few tens of digital gates [8]. They rely on the total delay of a closed loop of digital delay cells.…”

Section: Introductionmentioning

confidence: 99%

Single Event Transients in CMOS Ring Oscillators

Prinzie

Smedt

2019

Electronics

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In this paper, a time-variant analysis is made on Single-Event Transients (SETs) in integrated CMOS ring oscillators. The Impulse Sensitive Function (ISF) of the oscillator is used to analyze the impact of the relative moment when a particle hits the circuit. The analysis is based on simulations and verified experimentally with a Two-Photon Absorption (TPA) laser setup. The experiments are done using a 65 nm CMOS test chip.

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A Low Power Fast Ethernet Physical Layer Transceiver

Buhr

Kreissig

et al. 2019

2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

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Low Power 16 Phase Ring Oscillator and PLL for Use in sub-ns Time Synchronization over Ethernet

Cited by 7 publications

References 5 publications

Low power analogue equaliser with adaptive digital tuning for fast ethernet

Low power analogue equaliser with adaptive digital tuning for fast ethernet

Single Event Transients in CMOS Ring Oscillators

A Low Power Fast Ethernet Physical Layer Transceiver

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