A Low Power Fast Ethernet Physical Layer Transceiver

Buhr, Simon; Xu, Xin; Kreissig, Martin; Ellinger, Frank

doi:10.1109/icecs46596.2019.8964920

Cited by 3 publications

(3 citation statements)

References 10 publications

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“…5 Unshielded Twisted-wire Pair (UTP) cable defines as encoding technique the combination of 4B5B, and MLT-3. In addition, 100Base-TX requires a scrambling stage, which is meant to randomize the digital signal to further reduce radiated emissions [9], [10]. The encoding stage schematic diagram is reported in Fig.…”

Section: Mlt-3 Encoding Technique Overviewmentioning

confidence: 99%

Circuit Modeling of Fast Ethernet Signal for EMC and SI Analysis

Illiano,

Liu,

et al. 2023

2023 International Symposium on Electromagnetic Compatibility – EMC Europe

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The 100BASE-TX Fast Ethernet is the most widely adopted standard in residential sector today. This standard requires the signal generated by the physical layer to be encoded with a Multi-Level Transmit (MLT)-3 modulation, which shifts the spectrum energy to low frequencies. Improper design of the Fast Ethernet system causes Electromagnetic Compatibility (EMC) and Signal Integrity (SI) related issues that occur in real-world applications, yet an efficient circuit model for MLT-3 signal generation, which is crucial for system EMC and SI performance evaluation, is not available in the literature. This paper fills this gap by presenting a circuit model that simulates the behavior of the physical layer for Fast Ethernet applications. By tuning the sampling frequency parameter of the circuit and adding an RC filter, the circuit model mimics the time-domain and frequency-domain characteristics of a measured MLT-3 signal, allowing to effectively address the testing and optimization of EMC and SI issues in Fast Ethernet systems.

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Section: Mlt-3 Encoding Technique Overviewmentioning

confidence: 99%

Circuit Modeling of Fast Ethernet Signal for EMC and SI Analysis

Illiano,

Liu,

et al. 2023

2023 International Symposium on Electromagnetic Compatibility – EMC Europe

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“…(m/sec). (6) The attenuation (𝐴𝐴 𝑡𝑡𝑘𝑘 ) for 100-m cable is expressed in [12] and [15] as This research, therefore, provides a method that can be used to simulate the channel insertion loss of structured cabling standard and also study the effects of patch cords and cable lengths on the insertion loss. Different channel configurations were compared with each other to observe the effect on the insertion loss.…”

Section: A Category 8 Channel Configurationmentioning

confidence: 99%

“…Insertion loss (attenuation) is a measure of the decrease in signal strength along the length of a transmission line or channel [5]. When it comes to transmitting data over twisted pair wired channels, Ethernet is the technology widely used [6]. Ethernet is now used in Internet of Things for homes, industries, public places, etc.…”

Section: Introductionmentioning

confidence: 99%

Modeling the Insertion Loss of Structured Ethernet Cabling Standard using the Scattering Parameters

Ogundapo

Nche

2022

ACES Journal

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A method of simulating the insertion loss of different channel configurations of structured Ethernet cabling with reference to standard specifications is presented. The method can aid cable engineers in the study of the performance of Ethernet cabling systems during standardization in order to have a view of what to expect in real life. The paper considered the standard category 8 cabling system as a case study. The method presented used the scattering parameters implemented in Matrix Laboratory (MATLAB) to model the insertion loss of standard category 8 cabling system. The insertion loss simulation results provided good agreements with the standard category 8 cabling system. The method presented will serve as a basis to cable engineers who want to study future structured cabling systems under standardization to aid the design of prototype Ethernet cables.

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Design and Test of Offset Quadrature Phase-Shift Keying Modulator with GF180MCU Open Source Process Design Kit

Mascorro-Guardado,

Ortega-Cisneros,

Baungarten-Leon

et al. 2024

Electronics

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This article explores the evolution of integrated circuits (ICs), highlighting the fundamental role of open source Electronic Design Automation (EDA) tools in their development. It describes the IC’s design flow, differentiating between Front-end and Back-end design stages, and details the process of implementing the digital stage in offset quadrature phase-shift keying (OQPSK) modulation in an IC, including its hardware description language (HDL), the implementation test in the field-programmable gate array (FPGA), and the physical layout using the first manufactured open source process design kits (PDKs) in Global Foundries’ 180 nm, as well as the use of OpenLane and Caravel. To conclude, the results of the physical tests obtained from the digital modulation are presented, as well as the performance of the raised cosine shaping filter.

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A Low Power Fast Ethernet Physical Layer Transceiver

Cited by 3 publications

References 10 publications

Circuit Modeling of Fast Ethernet Signal for EMC and SI Analysis

Circuit Modeling of Fast Ethernet Signal for EMC and SI Analysis

Modeling the Insertion Loss of Structured Ethernet Cabling Standard using the Scattering Parameters

Design and Test of Offset Quadrature Phase-Shift Keying Modulator with GF180MCU Open Source Process Design Kit

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