Circuit Modeling of Fast Ethernet Signal for EMC and SI Analysis

Abstract

The 100BASE-TX Fast Ethernet is the most widely adopted standard in residential sector today. This standard requires the signal generated by the physical layer to be encoded with a Multi-Level Transmit (MLT)-3 modulation, which shifts the spectrum energy to low frequencies. Improper design of the Fast Ethernet system causes Electromagnetic Compatibility (EMC) and Signal Integrity (SI) related issues that occur in real-world applications, yet an efficient circuit model for MLT-3 signal generation, which is crucial for system EMC and SI performance evaluation, is not available in the literature. This paper fills this gap by presenting a circuit model that simulates the behavior of the physical layer for Fast Ethernet applications. By tuning the sampling frequency parameter of the circuit and adding an RC filter, the circuit model mimics the time-domain and frequency-domain characteristics of a measured MLT-3 signal, allowing to effectively address the testing and optimization of EMC and SI issues in Fast Ethernet systems.