Low-Leakage Flip-Flops Based on Dual-Threshold and Multiple Leakage Reduction Techniques

Zhang, Weiqiang; Su, Li; Li, Linfeng; Hu, Jianping

doi:10.1142/s0218126611007128

Cited by 16 publications

(7 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…As we have proposed SRs out of DFF, we have taken similar low-power DFFs for building register designs. They are named as follows: transmission gate SR developed from a conventional transmission gate FF (TGSR) (Zhang et al , 2011); topologically compressed SR made out of topologically compressed FF (TCSR) (Kawai et al , 2014); logic structure reduction technique SR developed from logic structure reduction technique FF (LRSR) (Lin et al , 2017); SR made from a dynamic FF designed by author Gago (GagoSR) (Gago et al , 1993); pulse-triggered SR from pulse-triggered FF (PTSR) (Karimi et al , 2018); lector-based clock gating SR developed from LBCG FF (LBCG-SR) (Bhattacharjee and Majumder, 2018); scan SR developed from Scan FF (SC-SR) (Razmdideh et al , 2015); 18 transistor SRs made from 18TFF (18TSR) (Cai et al , 2018); and implicit pulse-triggered FF with clock gating and pull-up control scheme SR developed from IP-CGPC FF (IP-CGPCSR) (Geng et al , 2016). …”

Section: Resultsmentioning

confidence: 99%

Power and area-efficient register designs involving EHO algorithm

Sabu

Batri

2020

View full text Add to dashboard Cite

Purpose This paper aims to design three low-power and area-efficient serial input parallel output (SIPO) register designs, namely, transistor count reduction technique shift register (TCRSR), series stacking in TCR shift register (S-TCRSR) and forced stacking of transistor in TCR shift register (FST in TCRSR). Shift registers (SR) are the basic building blocks of all types of digital applications. The performance of all the designs has been improved through one of the metaheuristic algorithms named elephant herding optimization (EHO) algorithm and hence suited for low-power very large scale integration (VLSI) applications. It is for the first time that the EHO algorithm is implemented in memory elements. Design/methodology/approach The registers together with clock network consume 18-36 percentage of the total power consumption of a microprocessor. The proposed designs are implemented using low-power and high-performance double edge-triggered D flip-flops with least count of clocked transistors involving transmission gate. The second and third register designs are developed from the modified version of the first one employing series and forced stacking, thereby reducing static power because of sub-threshold leakage current. The performance parameters such as power-delay-product (PDP) and leakage power are further optimized using the EHO algorithm. A greater reduction in power is achieved in all the designs by utilizing the EHO algorithm. Findings All the designs are simulated at a supply voltage of 1 V/500 MHz when the input switching activity is 25 percentage in Cadence Virtuoso using 45 nm CMOS technology. Nine recently proposed SR designs are simulated in the same conditions, and the performance has been compared with the proposed ones. The simulated results prove the excellence of proposed designs in different performance parameters like leakage power, energy-delay-product (EDP), PDP, layout area compared with the recent designs. The PDPdq value has a reduction of 95.9per cent (TCRSR), 96.6per cent (S-TCRSR) and 97per cent (FST in TCRSR) with that of a conventional shift register (TGSR). Originality/value The performance of proposed low-power SR designs is enhanced using EHO algorithm. The optimized performance results have been compared with a few optimization algorithms. It is for the first time that EHO algorithm is implemented in memory elements.

show abstract

Section: Resultsmentioning

confidence: 99%

Power and area-efficient register designs involving EHO algorithm

Sabu

Batri

2020

View full text Add to dashboard Cite

show abstract

“…With the increasing demand for battery-operated mobile platforms like laptops, and biomedical applications that require ultra-low power dissipations, low power designs have become more and more important. IC designers work hard on high performance with low power dissipation and small area [3][4][5].…”

Section: Introductionmentioning

confidence: 99%

Research on Ring Fire Diagnosis of DC Motor Based on Discrete Wavelet Lipschitz Index

Zhao-ping¹,

Yang²,

Tang³

et al. 2015

TOEEJ

View full text Add to dashboard Cite

Scaling supply voltage of FinFET circuits is an efficient method to achieve low power dissipation. Superthreshold FinFET logic circuits can attain low power consumption with favorable performance, because FinFET devices operating on medium strong inversion regions can provide better drive strength than conventional CMOS transistors. The supply voltage of the super-threshold circuit is much larger than threshold voltage of the transistors, but it is lower than normal standard supply voltage. In this paper, basic FinFET logic gates based on static logic, DCVSL (Differential Cascode Voltage Switch Logic), PTL (Pass Transistor Logic), and TG (Transmission Gate) logic styles operating on medium strong inversion regions are investigated in terms of power consumption and delay. All circuits are simulated with HSPICE at a PTM (Predictive Technology Model) 32nm FinFET technology. The simulation results show that superthreshold FinFET logic gates operating on medium strong inversion regions attain about 41% power reduction with a penalty of only about 23%.

show abstract

“…With the increasing demand for battery-operated electronic products that require ultra-low energy dissipations, high performance with energy-efficient designs have become more and more important [3]. In recent decades of years, IC designers and researcher have been working on faster operation speed with lower power dissipations and smaller chip area [4][5][6].…”

Section: Introductionmentioning

confidence: 99%

Low-power Super-threshold FinFET Domino Logic Circuits for High- Speed Applications

Bo¹,

Hu²,

Li³

et al. 2014

TOAUTOCJ

View full text Add to dashboard Cite

Domino logic circuits have faster operating speed than commonly used static logic ones, because they have lower input capacitances and no contention during transition. However, Domino logic circuits have more power dissipation than static logic ones, since their clock tress with high switch activity dissipates large energy. A low-power superthreshold computing scheme is proposed to reduce power dissipations of FinFET Domino logic circuits. The pull-down transistors of all FinFET Domino circuits are configured in parallel, and thus improve operating speed. Unlike nearthreshold circuits, super-threshold ones are supplied by much a larger supply voltage than the threshold voltage, but it is lower than the standard supply voltage. Super-threshold FinFET logic circuits can attain low power consumption with favorable performance, because FinFET devices operating on medium strong inversion regions can provide better drive strength than conventional CMOS ones. The basic Domino logic gates are compared with static logic ones in terms of energy consumption, delay, energy delay product (EDP), and maximum operation frequency with different voltages from near-threshold to super-threshold regions. All circuits are simulated with HSPICE at a PTM (Predictive Technology Model) 32nm FinFET technology. The results show that the Domino gates can operate faster than static ones. In addition, it is also shown that Domino gates exhibit the best EDP in super-threshold regions (about 700mV). Compared with the standard supply voltage of 1.0 V, the Domino gates supplied by 0.8V can attain energy reductions of more than 38.3% with a small performance penalty of about 14%.

show abstract

Low-Leakage Flip-Flops Based on Dual-Threshold and Multiple Leakage Reduction Techniques

Cited by 16 publications

References 1 publication

Power and area-efficient register designs involving EHO algorithm

Power and area-efficient register designs involving EHO algorithm

Research on Ring Fire Diagnosis of DC Motor Based on Discrete Wavelet Lipschitz Index

Low-power Super-threshold FinFET Domino Logic Circuits for High- Speed Applications

Contact Info

Product

Resources

About