Power and area-efficient register designs involving EHO algorithm

Abstract

Purpose This paper aims to design three low-power and area-efficient serial input parallel output (SIPO) register designs, namely, transistor count reduction technique shift register (TCRSR), series stacking in TCR shift register (S-TCRSR) and forced stacking of transistor in TCR shift register (FST in TCRSR). Shift registers (SR) are the basic building blocks of all types of digital applications. The performance of all the designs has been improved through one of the metaheuristic algorithms named elephant herding optimization (EHO) algorithm and hence suited for low-power very large scale integration (VLSI) applications. It is for the first time that the EHO algorithm is implemented in memory elements. Design/methodology/approach The registers together with clock network consume 18-36 percentage of the total power consumption of a microprocessor. The proposed designs are implemented using low-power and high-performance double edge-triggered D flip-flops with least count of clocked transistors involving transmission gate. The second and third register designs are developed from the modified version of the first one employing series and forced stacking, thereby reducing static power because of sub-threshold leakage current. The performance parameters such as power-delay-product (PDP) and leakage power are further optimized using the EHO algorithm. A greater reduction in power is achieved in all the designs by utilizing the EHO algorithm. Findings All the designs are simulated at a supply voltage of 1 V/500 MHz when the input switching activity is 25 percentage in Cadence Virtuoso using 45 nm CMOS technology. Nine recently proposed SR designs are simulated in the same conditions, and the performance has been compared with the proposed ones. The simulated results prove the excellence of proposed designs in different performance parameters like leakage power, energy-delay-product (EDP), PDP, layout area compared with the recent designs. The PDPdq value has a reduction of 95.9per cent (TCRSR), 96.6per cent (S-TCRSR) and 97per cent (FST in TCRSR) with that of a conventional shift register (TGSR). Originality/value The performance of proposed low-power SR designs is enhanced using EHO algorithm. The optimized performance results have been compared with a few optimization algorithms. It is for the first time that EHO algorithm is implemented in memory elements.

Adaptive hybrid arbiter design for real-time traffic-aware scheduling

“…As a result of taking up these challenges, researchers have come up with the development of efficient and sophisticated system-on-chip (SoC) and multiprocessor system-on-chip (MP-SoC) architectures. Low power and area-efficient system design techniques incorporated with these systems are expected to revolutionize the way we think about digital systems (Wolf et al, 2008;Khan and Mir, 2017;Khan and Mir, 2019;Sabu and Batri, 2020). However, traditional approach of interconnection of modules inside these complex systems is not feasible.…”