Low-frequency noise in junctionless multigate transistors

Abstract

Low-frequency noise in n-type junctionless multigate transistors was investigated. It can be well understood with the carrier number fluctuations whereas the conduction is mainly limited by the bulk expecting Hooge mobility fluctuations. The trapping/release of charge carriers is related not only to the oxide-semiconductor interface but also to the depleted channel. The volume trap density is in the range of 6-30 x 10(16) cm(-3) eV(-1), which is similar to Si-SiO2 bulk transistors and remarkably lower than in high-k transistors. These results show that the noise in nanowire devices might be affected by additional trapping centers. (C) 2011 American Institute of Physics. (doi:10.1063/1.3569724

Silicon-on-insulator (SOI) junctionless transistors

“…These are due to the trapping/release of charge carriers not only at the oxide-semiconductor interface but also in the depleted channel, which induce time-dependent variations of the cross-section of the neutral (undepleted) bulk conduction channel. Overall, trigate JLTs achieve noise levels similar to those in IM devices with high-quality gate oxide interfaces (Jang et al , 2011). In GAA junctionless FETs, all transport below fl atband is due to carriers in the center of the nanowire, far from any interface.…”

Modeling Channel Thermal Noise and Induced Gate Noise in Junctionless FETs

“…Obviously, relation (14) will be less accurate as the drain to source potential is increased. Merging (13) and (14) leads to an analytical model for PSD of cross-correlation noise The proposed approach gives an accurate description of crosscorrelation noise when the drain to source potential remains relatively small, i.e., below 100 mV [ Fig. 5(a), (b), (e), and (f)], without introducing any fitting parameter.…”

“…Although there have been quite a lot of efforts to model the dc characteristics of JL devices [4]- [10], not so much interest has been paid to ac modeling [11]- [13], and even less for thermal noise, despite its relevance for RF design. Some investigations have been carried out for low-frequency noise by means of Synopsys technology computer-aided design (TCAD) simulations and experimental results [13]- [16], but there is still no explicit thermal noise model for this device, and no assessment against the regular inversion mode (IM) FET counterpart. To the best of our knowledge, two works [17] and [18] have been published on thermal noise modeling in JL devices, but no explicit solution was proposed (besides, noise was plotted with respect to the gate voltage, which hampers any comparison with regular FETs).…”

Effect of Interface Traps on the RTS Noise Behavior of Junctionless Nanowires

“…Considering the working mechanism of the JNT and its sensibility to this specific kind of noise, this work was proposed, focusing on how few traps with similar characteristics may affect the noise of the device and, consequently, its operation. Most papers presented in current literature about low frequency noise in Junctionless transistors [3][4][5][6] perform a qualitative noise analysis without correlating the obtained curves to the traps' characteristics, such as its cross section and activation energy. So that, the main goal of this work is to provide more information on the low frequency noise behavior of the JNT considering the RTS noise.…”