Low FPGA area multiplier blocks for full parallel FIR filters

Macpherson, K.N.; Stewart, Robert W.

doi:10.1109/fpt.2004.1393275

Cited by 6 publications

(6 citation statements)

References 9 publications

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“…The main reason why the proposed 6T adders can be plugged into the tree-based architecture for multiple operands merging 6 without disturbing the regularity is that it has an integer compression ratio of 2 (i.e., six inputs can be merged into three). This is one unique property that has not been found in numerous compressors such as (3,2), (5,3), or (7, 4)-compressors proposed previously in the literature. A compressor with an integer compression ratio can lead to a more regular structure as shown in the following example.…”

Section: Six-to-triple Compressormentioning

confidence: 82%

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Low-power adaptive FIR filter generator using bit-oriented structures

Lin

Huang

2006

IEE Proc., Circuits Devices Syst.

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In this paper we present a bit-oriented architecture for the digital Finite Impulse Response (FIR) filter with adaptive coefficients. Instead of using multipliers, the FIR operation is regarded as the summation of a larger number of operands. Our architecture utilizes two new word-level operand compressors, namely six-to-triple and six-to-double compressors. Both of these two compressors, multiple operands can be merged efficiently without long carry propagation. Using such compressors as the basic building blocks, an FIR can be implemented as a fast and regular structure that lends itself to automation. Experiments show that our FIR generator based on the proposed architecture could easily achieve a 44% power reduction as compared to the traditional high-speed transposed form.

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Section: Six-to-triple Compressormentioning

confidence: 82%

“…Note that in this work we focus on ASIC-based implementation. For FPGA-based implementation, different design consideration that takes into account the specific FPGA architecture is necessary in order to produce more area-efficient results [3].…”

Section: Resultsmentioning

confidence: 99%

Low-power adaptive FIR filter generator using bit-oriented structures

Lin

Huang

2006

IEE Proc., Circuits Devices Syst.

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“…We implement the H cub , RSG, and RAG-n algorithms in [11] using CλaSH, recommending the use of an H cub variant which limits the graph depth at the expense of the number of adders. This will generally result in smaller FPGA areas for fully pipelined MCM blocks due to the predetermined ratio of look-up tables to registers (1:2 for the RFSoC's architecture); an effect explored further in [9].…”

Section: B Polyphase Filter With Shared MCM Subfiltersmentioning

confidence: 99%

Low-cost, High-speed Parallel FIR Filters for RFSoC Front-Ends Enabled by CλaSH

Ramsay

Crockett

Stewart

2021

2021 55th Asilomar Conference on Signals, Systems, and Computers

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We present a new low-cost, high-speed parallel FIR filter generator targeting the Xilinx Radio Frequency System on Chip (RFSoC) and direct RF sampling applications. We compose two existing approaches in a novel hierarchy: efficient parallelism with Fast FIR Algorithm (FFA) structures, and efficient multiplierless FIR implementations with H cub . The resource usage advantages (in both area and type) are compared with similar output from the traditional architecture, exemplified by vendor tools, as well as the H cub -based filters without the FFA optimisation. Although these techniques are well studied individually in the literature, they have not enjoyed mainstream use as their structural complexity proves awkward to capture with traditional Hardware Description Languages (HDLs). This work continues a discussion of the use of functional programming techniques in hardware description, highlighting the benefits of having easily composable circuit generators.

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“…The FIR filter is generally implemented in a non-recursive way, which guarantees a stable filter [2]. FIR filter design essentially consists of two parts:-…”

Section: Fir Filter Design Techniquesmentioning

confidence: 99%

High Speed FPGA Implementation of FIR Filter for DSP Applications

Thakur¹,

Khare²

2013

IJMO

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Abstract-Signal processing ranks among the most demanding applications of digital design concepts. It is a mature technology domain wherein the demands for enhanced performance and reduced resource utilization have risen exponentially over the years. Field Programmable Gate Array (FPGA) design technology has becoming the preferred platform for evaluating and implementing signal processing algorithms. The advantages of the FPGA approach to digital filter implementation include higher sampling rates than are available from traditional DSP chips, lower costs than an application specific integrated circuit (ASIC) for moderate volume applications, and more flexibility than the alternate approaches. Since many current FPGA architectures are in-system programmable, the configuration of the device may be changed to implement different functionality if required. This paper describes an approach to the implementation of digital filter based on field programmable gate arrays (FPGAs) which is flexible and provides performance comparable or superior to traditional approaches, lowpower, area-efficient re-configurable digital signal processing architecture that is tailored for the realization of arbitrary response Finite impulse response (FIR) filters.

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Low FPGA area multiplier blocks for full parallel FIR filters

Cited by 6 publications

References 9 publications

Low-power adaptive FIR filter generator using bit-oriented structures

Low-power adaptive FIR filter generator using bit-oriented structures

Low-cost, High-speed Parallel FIR Filters for RFSoC Front-Ends Enabled by CλaSH

High Speed FPGA Implementation of FIR Filter for DSP Applications

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