High Speed FPGA Implementation of FIR Filter for DSP Applications

Thakur, Rakhi; Khare, Kavita

doi:10.7763/ijmo.2013.v3.242

Cited by 23 publications

(10 citation statements)

References 3 publications

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“…In [4], the researchers provided a brief summary of electronic filters, their methods of enhancing their use over analog filters and their forms (FIR and IIR) and their use of FPGA. The numerous potential benefits of FIR filters are stressed, as the design of the FIR filter is easy and its frequency reaction is faster than the IIR filter and can be applied to any type of frequency.…”

Section: Background Workmentioning

confidence: 99%

Performance of Improved FIR filer using FPGA

Prasad. K*

2019

IJRTE

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A crucial part of the digital system is the FIR filter where its framework is robust and simple to connect. In this paper, a regular FIR filter and an optimized FIR filter were modeled using window functions. The FIR filter was designed and contrived by FPGA for digital signal filtering. Also in this paper, a regular FIR filter and an optimized FIR filter were built with window usability. The main characteristic of the application is the Xillinx ISE development suite program to build the FPGA data filter accelerator. The paper also simulates the hardware and software co-designed FIR filter and provides simulation findings about hardware assets and variations in quality compared to the standard and improved FIR filter

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Section: Background Workmentioning

confidence: 99%

Performance of Improved FIR filer using FPGA

Prasad. K*

2019

IJRTE

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“…In this design option, we use the same scheduling function s 3 . The time index associated with any point p is given by (31). The projection matrix corresponding to the linear projection direction d 2 is given by…”

Section: Design Option #4: Using S 2 = [1 1] and D 1 = [1 0] Tmentioning

confidence: 99%

Decimator systolic arrays design space exploration for multirate signal processing applications

Shoukry

Gebali

Agathoklis

2019

IET Circuits, Devices & Systems

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This study presents a new systolic array structure for a decimator that merges the antialiasing finite impulse response (FIR) filter with the downsampler. The development of the structure is based on a systematic methodology. Using this methodology, a dependence graph for the decimator was obtained that combined the antialiasing filter and the downsampler. Different data scheduling and projection operations were developed to obtain different proposed designs. Six systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation and compared with the other two well known decimator designs; namely, conventional design, in which the antialiasing filter is followed by a downsampling and the polyphase design, in which a commutator is followed by the polyphase antialiasing filter. Fieldprogrammable gate array implementations for the proposed and the other two designs confirm that the proposed decimator implementation outperforms in terms of area, speed, and power as the decimation factor increases regardless of the number of FIR filter coefficients.

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“…PSO gives the better solutions over GA, processing time of one iteration of PSO algorithm gives higher process speed for optimization problems rather than genetic algorithm [8]. Implementation of digital filers based on FPGA which is flexible, low power, low cast and area sufficient provide better performance and superior to traditional approach [9].…”

Section: Introductionmentioning

confidence: 99%

FPGA based Synthesize of PSO Algorithm and its Area-Performance Analysis

Harijan¹,

Shaikh²,

Arain³

et al. 2018

ijacsa

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Digital filters are the most significant part of signal processing that are used in enormous applications such as speech recognition, acoustic, adaptive equalization, and noise and interference reduction. It would be of great benefit to implement adaptive FIR filter because of self-optimization property, linearity and frequency stability. Designing FIR filter involves multi-modal optimization problems whereas conservative gradient optimization technique is not useful to design the filter. Hence, Particle Swarm Optimization (PSO) algorithm is more flexible and optimization technique based on population of particles in search space and alternative approach for linear phase FIR filter design. PSO improves the solution characteristic by giving a novel method for updating swarm's position and velocity vector. Set of optimized filter coefficients will be generated by PSO algorithm. In this paper, PSO based FIR Low pass filter is efficiently designed in MATLAB and further Xilinx System Generator tool is used to efficiently design, synthesize and implement FIR filter in FPGA using SPARTEN 3E kit. For an example specifications, output of PSO algorithm is obtained that is set of optimized coefficients whose response is approximating to the ideal response. Hence, functional verification of the proposed algorithm has been performed and the error between obtained filter and ideal filter is minimized successfully. This work demonstrates the effectiveness of the PSO algorithms in parallel processing environment as compared to the Remez Exchange algorithm.

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High Speed FPGA Implementation of FIR Filter for DSP Applications

Cited by 23 publications

References 3 publications

Performance of Improved FIR filer using FPGA

Performance of Improved FIR filer using FPGA

Decimator systolic arrays design space exploration for multirate signal processing applications

FPGA based Synthesize of PSO Algorithm and its Area-Performance Analysis

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