Low-energy neutron sensitivity of recent generation SRAMs

Arimani, J.M.; Simon, Guillaume; Poirot, P.

doi:10.1109/tns.2004.835080

Cited by 17 publications

(4 citation statements)

References 5 publications

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“…First of all, the sensitivity depends on the power supply values: the lower the power supply value, the higher the probability of an SEU [27], [32], [33]. Besides, other works have found a little dependence on the temperature [34].…”

Section: Factors Increasing the Probability Of An Seementioning

confidence: 99%

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Velazco

Franco

2007

2007 IEEE International Symposium on Industrial Electronics

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Abstract-New generation electronic devices have become more and more sensitive to the effects of the natural radiation coming from the surrounding environment. These radiation sources are cosmic rays and radioactive impurities, able to corrupt the content of memory cells or to induce transient pulses in combinational logic. The growing sensitivity seems to be related to two main factors: the lower and lower charge needed to define the logic levels in advanced devices and the increasing number of basic components inside the modern integrated circuits. In this paper, are described state-of-art techniques to mitigate these effects as well as typical tests to verify the radiation-tolerance of the devices and/or systems.

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Section: Factors Increasing the Probability Of An Seementioning

confidence: 99%

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Velazco

Franco

2007

2007 IEEE International Symposium on Industrial Electronics

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“…Thermal neutron-induced SEEs were reported for DRAMs and SRAMs containing BPSG in [1]- [3], and the 20% abundance of 10 B in the natural boron used in BPSG layers was identified as the culprit. Semiconductor foundries started to leave BPSG out of the manufacturing process at the 180-nm node and below, yet thermal neutron-induced SEEs have continued to be reported for modern components suspected to contain BPSG, such as 0.22-μm SRAMs [4]. Other modern components, such as the deep-submicrometer SRAM-based FPGAs described in [5], attribute thermal neutron-induced SEE sensitivity to 10 B introduced through other processing steps.…”

Section: Introductionmentioning

confidence: 99%

Thermal Neutron-Induced Single-Event Upsets in Microcontrollers Containing Boron-10

Auden

Quinn

Wender

et al. 2020

IEEE Trans. Nucl. Sci.

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Single-event upsets (SEUs) were measured in thermal neutron-irradiated microcontrollers with 65-and 130-nm-node static random-access memories (SRAMs). The suspected upset mechanism is charge deposition from the energetic byproducts of 10 B thermal neutron capture. Although elemental analysis confirmed that both microcontrollers contain 10 B, only the 65-nm node microcontroller exhibited a strong response to thermal neutrons. Monte Carlo simulations were performed to investigate the effects of 11 B enrichment on thermal neutroninduced SEUs in a 65-nm SRAM node when boron is present in the p-type well, p-type source and drain, or tungsten plug. Simulations indicate that the byproducts of 10 B(n, α) 7 Li reactions are capable of generating sufficient charge to upset a 65-nm SRAM. The highest amount of charge deposition from 10 B(n, α) 7 Li reaction byproducts occurs when natural boron is used to dope the p-type source and drain regions. Simulations also show that the SEU cross section is nonnegligible when 11 B-enriched boron is used for doping.

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“…[4,5] Moreover, the neutron-induced SEU sensitivity of submicron SRAMs was investigated by using mono-energetic and fission neu-tron beams. [6] With the scaling down of the technology node, neutron-induced SEU effects on nanometric SRAMs were studied. [7,8] The simulation approaches based on Monte-Carlo method have been widely developed to analyze the neutroninduced SEU effects.…”

Section: Introductionmentioning

confidence: 99%

Single event upset on static random access memory devices due to spallation, reactor, and monoenergetic neutrons*

Jin¹,

Chen²,

Li³

et al. 2019

Chinese Phys. B

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This paper presents new neutron-induced single event upset (SEU) data on the SRAM devices with the technology nodes from 40 nm to 500 nm due to spallation, reactor, and monoenergetic neutrons. The SEU effect is investigated as a function of incident neutron energy spectrum, technology node, byte pattern and neutron fluence rate. The experimental data show that the SEU effect mainly depends on the incident neutron spectrum and the technology node, and the SEU sensitivity induced by low-energy neutrons significantly increases with the technology downscaling. Monte–Carlo simulations of nuclear interactions with device architecture are utilized for comparing with the experimental results. This simulation approach allows us to investigate the key parameters of the SEU sensitivity, which are determined by the technology node and supply voltage. The simulation shows that the high-energy neutrons have more nuclear reaction channels to generate more secondary particles which lead to the significant enhancement of the SEU cross-sections, and thus revealing the physical mechanism for SEU sensitivity to the incident neutron spectrum.

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Low-energy neutron sensitivity of recent generation SRAMs

Cited by 17 publications

References 5 publications

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Single Event Effects on Digital Integrated Circuits: Origins and Mitigation Techniques

Thermal Neutron-Induced Single-Event Upsets in Microcontrollers Containing Boron-10

Single event upset on static random access memory devices due to spallation, reactor, and monoenergetic neutrons*

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