Low-energy inference machine with multilevel HfO<sub>2</sub> RRAM arrays

Milo, Valerio; Zambelli, Cristian; Olivo, P.; Pérez, Eduardo; Ossorio, Óscar G.; Wenger, Ch.; Ielmini, Daniele

doi:10.1109/essderc.2019.8901818

Cited by 4 publications

(3 citation statements)

References 12 publications

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“…CiM exploits memory array structure to achieve MAC operation that most consumes computation resources in neural networks. 8) CiM with NVM such as ReRAM 22) is suitable for achieving in-sensor computing because the processor can be integrated with the sensor by 3D stacking. The structure of CiM is described in the right part of Fig.…”

Section: Nvm Device Non-ideality In Cimmentioning

confidence: 99%

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Higuchi¹,

Kobayashi²,

Misawa³

et al. 2023

Jpn. J. Appl. Phys.

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This paper proposes tiny and error tolerant Convolutional LSTM (ConvLSTM) for event-based vision sensor (EVS) data processing with Computation-in-Memory (CiM) that utilizes ReRAM. To handle the event data by ConvLSTM, the type and parameter of event representation are optimized to pre-process event data. To realize tiny and error tolerant ConvLSTM CiM, reduction of the bit precision and error tolerance in each ConvLSTM layer and weight are considered. On the other hand, reducing the bit precision degrades inference accuracy and error tolerance. ReRAM has non-idealities such as conductance variation and worn out by Set/Reset cycles that induces bit inversion. Thus, bit error rate at each Set/Reset cycles are investigated, and the bit precision of the weight is optimized to accept bit error rate of 0.1% in simulation. The proposed tiny ConvLSTM can reduce the size of memory by 91% compared with non-optimized ConvLSTM of that weight is represented in 32-bit precision.

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Section: Nvm Device Non-ideality In Cimmentioning

confidence: 99%

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Higuchi¹,

Kobayashi²,

Misawa³

et al. 2023

Jpn. J. Appl. Phys.

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“…1,2) CiM has several advantages over conventional von Neumann computer architectures, including high throughput processing and low power consumption for DNNs. [3][4][5][6][7][8]9) Several CiM macros utilize emerging nonvolatile memories with multi-level cell (MLC). [10][11][12] On the other hand, the device non-idealities of CiM such as conductance variation and drift affect inference accuracy.…”

Section: Introductionmentioning

confidence: 99%

Computation-in-memory simulation platform to investigate inference accuracy degradation by device non-ideality interactions in deep neural network applications

Higuchi

Matsui

Misawa

et al. 2022

Jpn. J. Appl. Phys.

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This paper proposes a comprehensive computation-in-memory (CiM) simulation platform. The platform has the capability to emulate the degradation of inference accuracy caused by device non-ideality. In this paper, the effect of non-ideality by assuming non-volatile memory devices such as PRAM, ReRAM, MRAM, and FeFET in CiM were investigated. As the device is non-ideality, multi-level cell operation, conductance variation during verify-program, data retention error, sense amplifier offset, read current fluctuation, and device failure are considered. First, the acceptable amount of a single non-ideality was investigated. The results address that the conductance shift has much more of an adverse impact than conductance variation on inference accuracy in CiM. In the second place, interaction among multiple device non-idealities were also comprehensively investigated. The platform reveals paradoxical results that the inference accuracy of the combination of uniform shift and low conductance asymmetric error is higher than that of a single low conductance asymmetric error under specific conditions.

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“…In a previous paper [26], we contributed in this regard by defining several reliable conductive levels in monolayer Al-doped HfO 2 RRAM devices integrated in 4-kbit arrays by tuning two parameters of the relative simple programming algorithm known as multi-level incremental step pulse with verify algorithm (M-ISPVA). This multi-level approach was successfully employed in implementing a 2-layer feedforward neural network for the classification of the MNIST dataset [27,28]. Although similar studies can be found elsewhere [15,[29][30][31], none of them evaluate how the programming parameters used to define the synaptic weights in the RRAM array impact the results obtained by the VMM operations and, hence, on the accuracy of the corresponding DNN.…”

Section: Introductionmentioning

confidence: 99%

Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing

et al. 2021

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Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1 k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8 × 8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters.

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Low-energy inference machine with multilevel HfO₂ RRAM arrays

Cited by 4 publications

References 12 publications

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Computation-in-memory simulation platform to investigate inference accuracy degradation by device non-ideality interactions in deep neural network applications

Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing

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Low-energy inference machine with multilevel HfO2 RRAM arrays

Cited by 4 publications

References 12 publications

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Tiny and error-tolerant ConvLSTM for event-based vision sensor with optimized event representation and ReRAM computation-in-memory

Computation-in-memory simulation platform to investigate inference accuracy degradation by device non-ideality interactions in deep neural network applications

Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing

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Low-energy inference machine with multilevel HfO₂ RRAM arrays