This paper proposes a comprehensive computation-in-memory (CiM) simulation platform. The platform has the capability to emulate the degradation of inference accuracy caused by device non-ideality. In this paper, the effect of non-ideality by assuming non-volatile memory devices such as PRAM, ReRAM, MRAM, and FeFET in CiM were investigated. As the device is non-ideality, multi-level cell operation, conductance variation during verify-program, data retention error, sense amplifier offset, read current fluctuation, and device failure are considered. First, the acceptable amount of a single non-ideality was investigated. The results address that the conductance shift has much more of an adverse impact than conductance variation on inference accuracy in CiM. In the second place, interaction among multiple device non-idealities were also comprehensively investigated. The platform reveals paradoxical results that the inference accuracy of the combination of uniform shift and low conductance asymmetric error is higher than that of a single low conductance asymmetric error under specific conditions.