Optimization of Multi-Level Operation in RRAM Arrays for In-Memory Computing

Abstract

Accomplishing multi-level programming in resistive random access memory (RRAM) arrays with truly discrete and linearly spaced conductive levels is crucial in order to implement synaptic weights in hardware-based neuromorphic systems. In this paper, we implemented this feature on 4-kbit 1T1R RRAM arrays by tuning the programming parameters of the multi-level incremental step pulse with verify algorithm (M-ISPVA). The optimized set of parameters was assessed by comparing its results with a non-optimized one. The optimized set of parameters proved to be an effective way to define non-overlapped conductive levels due to the strong reduction of the device-to-device variability as well as of the cycle-to-cycle variability, assessed by inter-levels switching tests and during 1 k reset-set cycles. In order to evaluate this improvement in real scenarios, the experimental characteristics of the RRAM devices were captured by means of a behavioral model, which was used to simulate two different neuromorphic systems: an 8 × 8 vector-matrix-multiplication (VMM) accelerator and a 4-layer feedforward neural network for MNIST database recognition. The results clearly showed that the optimization of the programming parameters improved both the precision of VMM results as well as the recognition accuracy of the neural network in about 6% compared with the use of non-optimized parameters.

Modulating the Filamentary-Based Resistive Switching Properties of HfO2 Memristive Devices by Adding Al2O3 Layers

“…Although the values of the on/off ratios are reduced in V2 and V3 memristive devices, the variability in the on and off state currents of the resistive switching operations are also considerably reduced as shown in Figures 7 and 8. This reduction in variability is one of the basic requirements of the memristive devices to utilize them for multi-level operation [48]. The memristive devices with a capability of multi-level operation are suitable for neuromorphic computing applications [49].…”

“…The mean values of the HRS currents increase with the thickness of the Al2O3 layers. The memory window (MW), which is essentially the on/off ratio of the memristive ments of the memristive devices to utilize them for multi-level operation [48]. The memristive devices with a capability of multi-level operation are suitable for neuromorphic computing applications [49].…”

Data-driven RRAM device models using Kriging interpolation

“…According to the authors, the specific implementation of this model is a SPICE sub-circuit with two terminal connections and a parameter for the selection of the device conductance state. The model was successfully used in circuit simulations of neural networks 68 . Kriging modeling could be potentially applied to model the means and standard deviations of the readout current as a function of the read voltage instead of the simple linear fit.…”

“…thus providing a comprehensive model capturing the device population behavior. This has direct applicability to identifying the most optimal programming scheme for the devices which can reduce the experimental variability observed 68 , and thus more realistically modeling RRAM-implemented weight updates in neural network simulations.…”

Short-Term to Long-Term Plasticity Transition Behavior of Memristive Devices with Low Power Consumption via Facilitating Ionic Drift of Implanted Lithium

“…The demand for data processing in computing systems is significantly increasing, as data processing has become more complicated due to the diversity of information types, and since new developments in technology, such as big data, deep learning artificial intelligence (AI), and the internet of things (IoT), are enabling us to access an enormous amount of information in real time. The von Neumann architecture, which is a modern computing system consisting of a control, arithmetic/logic, registers, and memory units, has critical disadvantages for managing massive data processing such as the inability to conduct parallel implementation, the Von Neumann bottleneck, and has high-power consumption due to the fact of sequential instruction processing [1][2][3][4][5][6][7][8].…”