Computation-in-memory simulation platform to investigate inference accuracy degradation by device non-ideality interactions in deep neural network applications

Abstract

This paper proposes a comprehensive computation-in-memory (CiM) simulation platform. The platform has the capability to emulate the degradation of inference accuracy caused by device non-ideality. In this paper, the effect of non-ideality by assuming non-volatile memory devices such as PRAM, ReRAM, MRAM, and FeFET in CiM were investigated. As the device is non-ideality, multi-level cell operation, conductance variation during verify-program, data retention error, sense amplifier offset, read current fluctuation, and device failure are considered. First, the acceptable amount of a single non-ideality was investigated. The results address that the conductance shift has much more of an adverse impact than conductance variation on inference accuracy in CiM. In the second place, interaction among multiple device non-idealities were also comprehensively investigated. The platform reveals paradoxical results that the inference accuracy of the combination of uniform shift and low conductance asymmetric error is higher than that of a single low conductance asymmetric error under specific conditions.

Assessment of inference accuracy and memory capacity of computation-in-memory enabled neural network due to quantized weights, gradients, input and output signals, and memory non-idealities

“…The second type of nonideality is uniform shift which is used to replicate the behavior of the data retention variation of the memory type. 19) Both of these non-idealities are introduced to the already trained neural network models, and the said nonideality is exclusively added to the weight matrix of the network. The errors due to non-ideality are not added to the signals, and as such this documentation remains a topic of future research.…”

“…One such disadvantage would be the type of non-ideality that is being introduced in the system by virtue of manufacturing or an inherent disadvantage due to the memory design itself. 19) A summary of the undesired behaviors incurred due to the incorporation of CiM in the system is summarized in Table I. It should be noted that the non-idealities are not necessarily detrimental to the inference accuracy for a constrained neural network i.e.…”

Influence of unique behaviors in an atomic switch operation on hardware-based deep learning

“…Impacts of these non-idealities have also been investigated in detail for practical use. 21) In this study, we focused on an atomic switch, [22][23][24][25] which shows stable analog resistance change over a wide range. 26) Atomic switch has some learning ability, [27][28][29][30] and it can be used for a synaptic device for the deep learning.…”