Low cost testing of high density logic components

Bassett, R.W.; Butkus, B.J.; Dingle, S.L.; Faucher, M.R.; Gillis, P.S.; Panner, J.H.; Petrovick, John G.; Wheater, D.L.

doi:10.1109/test.1989.82339

Cited by 34 publications

(9 citation statements)

References 8 publications

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“…IBM's unique I/O wrap test features support a very cost-effective reduced pin count test (RPCT) approach for wafer sort, where only a subset of the chip I/Os needs to be contacted [132], [133]. The unique boundary scan implementation facilitates at-speed wrap-around testing at wafer sort and DC parametric testing of the I/Os at final (package-level) test.…”

Section: ) Embedded Memory and Macro Testmentioning

confidence: 99%

EDA in IBM: past, present, and future

Darringer

Davidson

Hathaway

et al. 2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Throughout its history, from the early four-circuit gate-array chips of the late 1960s to today's billion-transistor multichip module, IBM has invested in tools to support its leading-edge technology and high-performance product development. The combination of demanding designs and close cooperation among product, technology, and tool development has given rise to many innovations in the electronic design automation (EDA) area and provided IBM with a significant competitive advantage. This paper highlights IBM's contributions over the last four decades and presents a view of the future, where the best methods of multimillion gate ASIC and gigahertz microprocessor design are converged to enable highly productive system-on-a-chip designs that include widely diverse hardware and software components.

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Section: ) Embedded Memory and Macro Testmentioning

confidence: 99%

EDA in IBM: past, present, and future

Darringer

Davidson

Hathaway

et al. 2000

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Access to all other functional pins is achieved via the boundaryscan chain. First use of RPCT with LSSD boundary-scan was re-ported by IBM to enable the use of low-cost ATE for ASICs [8]. Since then, several extensions have been made to the basic RPCT technique.…”

Section: Prior Workmentioning

confidence: 99%

“…The other way to increase the number of sites is to narrow down the SOC-ATE interface, i.e., the number of SOC terminals that needs to be contacted during testing. Reduced-Pin-Count-Test (RPCT) [8,9,4] is a well-known DfT technique that does exactly this. This paper focuses on designing and optimizing an on-chip test infrastructure (DfT) to facilitate high-throughput multi-site wafer testing of large SOCs.…”

Section: Introductionmentioning

confidence: 99%

On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips

Goel

Marinissen

Design, Automation and Test in Europe

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“…RPCT is effective for designs with a small number of scan pins [2]. However, IC designs often incorporate multiple-scan chains to reduce testing time.…”

Section: Rpct Based On Test Data Compressionmentioning

confidence: 99%

“…Reduced pin-count test (RPCT) is a well-known technique for reducing the number of integrated circuit (IC) pins that have to be contacted by the tester [2,3]. RPCT requires full-scan design and boundary scan access to the £ This research was supported in part by the National Science Foundation under grant number CCR-9875324.…”

Section: Introductionmentioning

confidence: 99%