Low-Cost Online Testing of Asynchronous Handshakes

Shang, Delong; Yakovlev, Alex; Burns, Frank; Xia, Fei; Bystrov, A.

doi:10.1109/ets.2006.31

Cited by 18 publications

(19 citation statements)

References 10 publications

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“…Thus, any fault, which affects the control logic signals, typically leads to violations of handshake protocol. In [4], such faults have been classified as order violation faults or delay faults.…”

Section: Fault Modelsmentioning

confidence: 99%

A survey about testing asynchronous circuits

Zeidler

Krstić

2015

2015 European Conference on Circuit Theory and Design (ECCTD)

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Even though the asynchronous design methodology is considered to be a promising solution to upcoming challenges of designing complex integrated circuits (ICs), it is not widely accepted by the industry. Besides the lack of mature design tools, a further key inhibitor of using this design style is the widespread assumption that asynchronous circuits are difficult to test due to problems with system timing during test, nondeterminism, and difficulties with applying standard test approaches such as scan. However, there is a huge variety of approaches to handle these testing issues. This paper summarizes the different available test methodologies for asynchronous and globallyasynchronous locally-synchronous (GALS) designs and addresses their strengths and weaknesses. Moreover, it gives an overview of a methodology for testing based on the use of specific test processor, developed by IHP.

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Section: Fault Modelsmentioning

confidence: 99%

A survey about testing asynchronous circuits

Zeidler

Krstić

2015

2015 European Conference on Circuit Theory and Design (ECCTD)

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“…State encoding of 4 is ⟨111⟩. From state 4 we have a transition to state 3 on change of out from 1 to 0. Figure 12 illustrates the state graph for detecting 1 stuckon fault at C2 by FD-transitions ⟨ 11, 6⟩ and ⟨ 13, 8⟩.…”

Section: Des Detector Based Online Testermentioning

confidence: 99%

“…Most of the papers cited in the above discussion are for OLT of synchronous circuits and only a few of them [4,5,10] are applicable to asynchronous circuits. Now, we elaborate on these three works on OLT of asynchronous circuits and derive motivation of the present work.…”

Section: Introductionmentioning

confidence: 99%

“…Further, both being the same circuit, they are susceptible to similar nature of failures. The schemes reported in [4,5] basically work by checking whether the output of the asynchronous circuit maintains a predefined protocol (i.e., there is no premature or late occurrence of transitions). The checker circuit is implemented using David cells (DCs), Mutual Exclusion (Mutex) elements, C-elements, and logic gates.…”

Section: Introductionmentioning

confidence: 99%

“…The approach of self-checking design consists of encoding the circuit outputs using some error detecting code and then checking some code invariant property (e.g., Parity) [3][4][5]. Some examples are Parity codes [6], m-out-of-n codes [7], and so forth.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Discrete Event System Approach to Online Testing of Speed Independent Circuits

et al. 2015

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With the increase in soft failures in deep submicron ICs, online testing is becoming an integral part of design for testability. Some techniques for online testing of asynchronous circuits are proposed in the literature, which involves development of a checker that verifies the correctness of the protocol. This checker involves Mutex blocks making its area overhead quite high. In this paper, we have adapted the Theory of Fault Detection and Diagnosis available in the literature on Discrete Event Systems to online testing of speed independent asynchronous circuits. The scheme involves development of a state based model of the circuit, under normal and various stuck-at fault conditions, and finally designing state estimators termed as detectors. The detectors monitor the circuit online and determine whether it is functioning in normal/failure mode. The main advantages are nonintrusiveness and low area overheads compared to similar schemes reported in the literature.

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